Chip packaging method and packaging structure
A chip packaging structure and chip packaging technology, applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of increased difficulty of plastic packaging process, thickness limitation of stacked packaging structure, etc., to simplify process complexity, The effect of reducing thickness and simplifying process difficulty
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[0040] Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the various drawings, the same components are denoted by similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown. For simplicity, the structure obtained after several steps can be described in one figure. In the following, many specific details of the present invention are described, such as the structure, material, size, process and technique of each constituent part, for a clearer understanding of the present invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art. In addition, in this application, a chip refers to a semiconductor bare chip.
[0041] The present invention provides a chip packaging method, which mainly includes forming a first cavity in a substrate, and insta...
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