80results about How to "Simplify process complexity" patented technology

The invention discloses a high temperature superconductor coil and a winding technology of the high temperature superconductor coil. The high temperature superconductor coil comprises an epoxy barrel and a plurality of layers of coil units, wherein each coil unit is composed of a low temperature glue layer, a polyimide film layer and a superconduction strip layer which are arranged in sequence. According to the winding technology, firstly, a framework of the superconductor coil is well fixed, winding positions are marked, the surface of the framework is evenly coated with low temperature glue and wound with polyimide films, then polyimide belts are laid at equal intervals, tensioned and fixed, after a strip winding disc is prepared, the wire inlet end is fixed to the surface of the framework and is evenly and densely wound with a layer of superconduction strips, then the surface of each strip is coated with the low temperature glue and wound with a layer of polyimide films, the polyimide belts are tensioned and laid backwards, and all the operations are repeated until the whole coil is wound. It is guaranteed that certain prestress is applied to the superconduction strips, layer insulation is achieved through the polyimide films and the low temperature glue, and the winding technology is simple and effective on the basis of ensuring the performance of the strips effectively.

A 3-D Single Floating Gate Non-Volatile Memory (SFGNVM) device based on the 3-D fin Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The disclosed Non-Volatile Memory (NVM) device consists of a pair of semiconductor fins and one floating metal gate. The floating metal gate for storing electrical charges to alter the threshold voltage of the fin MOSFET crosses over the pair of semiconductor fins on top of coupling and tunneling dielectrics above the surfaces of the two semiconductor fins. One semiconductor fin with the same type impurity forms the control gate of the non-volatile memory device. The other semiconductor fin is doped with opposite type of impurity in the channel regions under the metal floating gate and with the same type of impurity in the source and drain regions on the sides of the crossed metal floating gate.