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Improved layout for device fabrication

A device and trench technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as reducing embedded gates

Active Publication Date: 2022-07-01
NEXPERIA BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, trench gate technology does pose some disadvantages when low voltage configurations are desired due to the need to reduce the width of the embedded gate

Method used

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  • Improved layout for device fabrication
  • Improved layout for device fabrication
  • Improved layout for device fabrication

Examples

Experimental program
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Embodiment Construction

[0014] It should be noted that the embodiments described herein use n-channel devices for example purposes only. Those skilled in the art will recognize that these embodiments can also be applied to p-channel devices. Many known manufacturing steps, components and connectors have been omitted from the description in order not to obscure the present invention.

[0015] figure 1 A schematic diagram depicting a cross-section of the device at an initial stage of fabrication. Wafer 100 is doped with n-type implants. An n-type or n+-type epitaxial layer 102 is implanted on the upper surface of the wafer 100 . It should be noted that the depths of the various layers shown in the figures are not drawn to scale. A p-type body region 104 is implanted on the upper surface of the epitaxial layer 102 . Then, n-type strips 106 are implanted at equal intervals in the Y direction according to the desired source spacing, the importance of which is discussed later in this document.

[001...

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Abstract

The present invention discloses a device and a method of manufacturing the device. The device includes: a semiconductor substrate; and a plurality of source lines formed on a surface of the semiconductor substrate. A plurality of source lines are arranged in both the X direction and the Y direction. The device further includes: a plurality of gate lines arranged above the source lines in the X direction of the plurality of source lines; a source contact line terminating in the Y direction with the plurality of source lines a source line connection; a gate contact line, which is connected to a plurality of gate lines; and a drain contact.

Description

Background technique [0001] Trench gate technology is often used to improve breakdown voltage characteristics in semiconductor devices, especially high voltage devices. In trench gate technology, the gate is buried vertically in the source and is usually separated by a spacer. Other advantages of trench gate technology include reducing junction gate field effect transistor (JFET) effects that may be undesirable in at least some applications. However, trench gate technology does present some disadvantages due to the need to reduce the width of the embedded gate when a low voltage configuration is desired. SUMMARY OF THE INVENTION [0002] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. [0003]...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/739H01L21/336H01L29/423
CPCH01L29/4236H01L29/66356H01L29/7391H01L29/407H01L29/4238H01L29/0696H01L29/0865H01L28/00H01L29/7813H01L29/66734H10B43/27
Inventor 史蒂文·托马斯·皮克
Owner NEXPERIA BV