Improved layout for device fabrication
A device and trench technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as reducing embedded gates
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[0014] It should be noted that the embodiments described herein use n-channel devices for example purposes only. Those skilled in the art will recognize that these embodiments can also be applied to p-channel devices. Many known manufacturing steps, components and connectors have been omitted from the description in order not to obscure the present invention.
[0015] figure 1 A schematic diagram depicting a cross-section of the device at an initial stage of fabrication. Wafer 100 is doped with n-type implants. An n-type or n+-type epitaxial layer 102 is implanted on the upper surface of the wafer 100 . It should be noted that the depths of the various layers shown in the figures are not drawn to scale. A p-type body region 104 is implanted on the upper surface of the epitaxial layer 102 . Then, n-type strips 106 are implanted at equal intervals in the Y direction according to the desired source spacing, the importance of which is discussed later in this document.
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