A method for FPGA to realize activation function in residual network

Abstract

The invention discloses a method for an FPGA to realize an activation function in a residual network. The method includes: each time entering a new convolutional layer of the residual network, reading the required activation function from the cache DDR of the FPGA chip Parameters; the data processed by the convolution module of the FPGA chip is read into the activation function processing module through the memory channel channel; in the activation function processing module, the data is sequentially substituted into the batch normalization function, scaling function and linear activation function Perform processing, and write the processed data back to the cache DDR through the memory channel channel. This method realizes reducing the I / O loss of data transmission between different activation functions.

Description

technical field [0001] The invention relates to the field of deep learning acceleration technology, in particular to a method for implementing an activation function in a residual network by an FPGA. Background technique [0002] At present, the rapid development of big data technology has greatly promoted the development of deep learning technology, and FPGA is one of the effective means to accelerate deep learning. In the usual convolutional neural network structure implemented by the CPU, different types of activation functions are in separate modules to achieve multiplexing and overloading of different network structures. It involves the use of the activation function in the residual network implemented by the FPGA, but the modules of the activation functions in the FPGA are not reusable, and the data between the modules is communicated through the memory channel (channel), so the chip cache is repeatedly read and written ( DDR) will inevitably bring efficiency loss on ...

AI Technical Summary

Problems solved by technology

It involves the use of the activation function in the residual network implemented by the FPGA, but the modules of the activation functions in the FPGA are not reusable, and the data between the modules is communicated through the memory channel (channel), so the chip cache is repeatedly read and written ( DDR) will inevitably bring efficiency loss on input and output, that is, the data transmission I / O loss between different activation functions is more

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