Noise filtering device, noise filtering method and programmable logic controller

Abstract

The application relates to a noise filtering device, a noise filtering method and a programmable logic controller. The noise filtering device is provided and comprises a signal receiving module, a noise filtering module and an output module, wherein the signal receiving module is configured to receive input signals to be processed via an external processing unit, the noise filtering module is configured to performing noise filtering operation on the input signals according to reference clock signals sent from the external processing unit, and the output module is configured to provide the filtered input signals to the external processing unit. Via use of the noise filtering device, the noise filtering method and the programmable logic controller disclosed in a solution of an embodiment of the application, filtering time can be chosen by a user in a fine-grained way in a large scope, and requirements of the user for the filtering device can be well met. A filtering device implementation circuit can be simplified, circuit cost can be lowered, and size reduction can be realized.

Description

technical field [0001] Embodiments of the present disclosure relate to the field of signal processing, and more particularly to noise filters, noise filtering methods, and programmable logic controllers. Background technique [0002] As is well known, Programmable Logic Controllers (PLCs) are widely used in industrial environments. Usually PLCs are provided with high-speed inputs such as high-speed operation signals of machines, also known as high-speed counter (HSC) inputs. Due to the influence of the external industrial environment, there will always be noise in the HSC input signal. [0003] In order to remove this noise, it is necessary to have a filter for each HSC input signal to perform corresponding noise filtering. Due to the high input frequency, almost all HSC input filters are implemented by hardware units, such as coprocessors or complex programmable logic devices (CPLD) / field programmable gate arrays (FGPA). figure 1 A schematic block diagram of a noise filt...

AI Technical Summary

Problems solved by technology

[0004] In the above traditional noise filtering scheme, the preset parameter table of the clock frequency divider (usually only including a dozen optional parameters) is limited, and correspondingly, the user's choice of filtering time is also limited

This is difficult to meet the requirements of various practical applications

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