IO circuit and memory

Abstract

The invention provides an IO circuit and memory. The IO circuit comprises a level switch module, which controls the circuit to stop working when the switch control signal is the default level and outputs an inversion signal of the digital signal when the switch control signal is not the default level; a first power supply switching module, which is connected to the first output terminal of the level switch module and a first power supply, converts the voltage swing of the inversion signal of the digital signal into the voltage of the first power supply, and carries out an inversion treatment on the converted signal; a first switch module, which is connected to a first power supply switch module, the power supply of the circuit, and an IO port, wherein when the signal after the inversion treatment is high level, the circuit is conductive, and the IO port is connected to the power supply of the circuit; and a second switch module, which is connected to the second output terminal of the level switch module, the IO port, and the ground, wherein when the inversion signal of the digital signal is high level, the circuit is conductive, and the IO port is grounded. The IO circuit can charge and discharge quickly. The charging performance is stable, the anti-interference performance is strong, and the happening rate of shoot-through is low.

Description

technical field [0001] The invention relates to the technical field of storage, in particular to an IO circuit and a memory. Background technique [0002] In FLASH (flash memory), read and write operations are the most basic operations. When FLASH outputs data b' to off-chip, it is necessary to apply IO circuit to generate "0" and "1" signals. figure 1 It is a structural schematic diagram of an existing IO circuit. [0003] figure 1 The IO circuit in the circuit has the following defects: when the IO port PAD' is charged from 0 to VDD', the impedance seen by the IO port PAD' is the drain end impedance of the PMOS transistor P1' and the NMOS transistor N1', and the impedance varies with different power supply voltages. VDD' is different. Therefore, under different power supply voltages, the charging capabilities of the IO circuits are different. In addition, if the level of data b' stops near the level of the flip point of PMOS transistor P1' and NMOS transistor N1', bot...

AI Technical Summary

Problems solved by technology

[0004] In view of the above problems, the purpose of the embodiments of the present invention is to provide an IO circuit and a memory to solve the problem that the existing IO circuit has a DC path and the charging capacity varies with the power supply voltage

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