Memory device, memory system and memory control method

Abstract

A memory device according to an embodiment of the present technology includes: a plurality of memory cells arranged in a matrix; a plurality of row wirings connected to one end of each memory cell; a plurality of column wirings connected to the other end of each memory cell; A first decoder circuit connected to each row wiring of the even-numbered rows; a second decoder circuit connected to each of the row wirings of the odd-numbered rows; a third decoder circuit connected to each of the column wirings of the even-numbered columns; and Quad decoder circuit, connected to each column wire of odd columns. The first decoder circuit, the second decoder circuit, the third decoder circuit, and the fourth decoder circuit are composed of mutually independent circuits.

Description

technical field

[0001] The present disclosure relates to a memory device including a decoder circuit, a memory system including the memory device, and a memory control method in the above-mentioned memory device. Background technique

[0002] In recent years, there has been a desire to expand the capacity for data storage of nonvolatile memories typified by resistance variable memories such as ReRAM (Resistive Random Access Memory). However, currently existing resistance variable memories utilizing access transistors result in an increase in footprint per unit cell. Therefore, expansion of capacity is not easy even in miniaturization using the same design rule, compared with, for example, a flash memory such as a NAND type. Meanwhile, in the case of using a so-called cross-point array structure, the footprint per unit cell becomes smaller, leading to the realization of capacity expansion. A cross-point array structure includes an arrangement of memory elements at intersect...

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