CPLD/FPGA-based clock frequency division module design method

A technology of clock frequency division and module design, applied in the field of frequency division, can solve the problems of high resource consumption, odd frequency division not 50% duty cycle, etc., to achieve the effect of less hardware resource consumption, flexible cutting, and fast update speed

Inactive Publication Date: 2018-01-09
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] For above-mentioned defect, the object of the present invention is to provide a kind of clock frequency division module design method

Method used

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  • CPLD/FPGA-based clock frequency division module design method
  • CPLD/FPGA-based clock frequency division module design method
  • CPLD/FPGA-based clock frequency division module design method

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0029] Example one:

[0030] Such as figure 2 As shown, the system clock on the main board is used as the reference input clock of the integer frequency division module. According to actual needs, the given module input parameters are used as the frequency division base N of the integer frequency division module. According to the frequency division base N, select the even frequency division module or the odd frequency division module. At the same time, turn off the other frequency division module, sample and divide the reference input clock to obtain the desired frequency division clock; according to the frequency division base N, select the even number The N-divided clock obtained by the frequency division module or the odd frequency division module is used as the output frequency division clock and used as the input clock of other modules.

[0031] Even frequency division module:

[0032] In order to divide the reference clock by an even number, the even number frequency division...

Example Embodiment

[0035] Embodiment two:

[0036] In order to verify the effectiveness of any integer frequency divider based on CPLD / FPGA, in the ModelSim environment, the frequency divider is verified by giving a different frequency division number N. The integer frequency divider achieves 4 (N is an even number) division Frequency simulation results such as Image 6 As shown, the simulation result of frequency division by 5 (N is an odd number) realized by the integer frequency divider is as follows Figure 7 Shown. It can be seen from the simulation results that the present invention is based on CPLD / FPGA for arbitrary integer 50% duty cycle frequency division clock modular realization method can output high-quality frequency division clock according to the N value, which verifies that the present invention is based on CPLD or FPGA for arbitrary integer The effectiveness of the 50% duty cycle divided clock.

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Abstract

The invention discloses a CPLD/FPGA-based clock frequency division module design method. The method comprises the following steps of 1: taking a system clock on a mainboard as a reference input clockof a clock frequency division module, and inputting a frequency division cardinal number N; 2: judging the parity of the frequency division cardinal number N, selectively using an even number frequency division module or a cardinal number frequency division module to perform frequency division, selecting the frequency division module, and turning off the other module; 3: performing sampling and frequency division on the reference input clock to obtain an expected frequency division clock; and 4: outputting the clock. The problems of high consumption of instantiated PLL IP core hardware resources in a CPLD/FPGA and non 50% duty ratio of odd number frequency division are solved.

Description

technical field [0001] The present invention relates to the technical field of frequency division methods, in particular to a design method for clock frequency division modules based on CPLD / FPGA. Background technique [0002] With the development of integrated circuits, the requirements for the clock are getting higher and higher, and the quality of the clock directly affects the performance of the entire system, and even affects the stability of the system. For high-end CPLD / FPGA chips, the clock with the desired frequency can be obtained by instantiating the PLL IP core, but there is a problem of consuming more hardware resources. And for different types of CPLD / FPGA chips, PLL IP cores generally cannot be transplanted. Therefore, it is of great significance to design a frequency divider that is versatile, consumes less hardware resources, and is easy to apply. [0003] In existing designs, most of the PLL IP cores are directly instantiated to obtain the desired frequen...

Claims

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Application Information

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IPC IPC(8): G06F17/50H03L7/18
Inventor 何业缘季冬冬张燕群
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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