34results about How to "Reduce hardware resource consumption" patented technology

The quantum computer comprises a quasi-one-dimensional layout superconducting quantum bit array, a control circuit and a reading circuit, The superconducting quantum bit array comprises two or more than two net-shaped units which are arranged in a net chain shape. The control circuit is coupled with the superconducting quantum bits through a microwave transmission line and used for controlling thesuperconducting quantum bits in a preset mode; And the reading circuit is coupled to one path of microwave signal line by a coplanar superconducting microwave resonant cavity for reading, is connected with an external circuit, and is used for reading the quantum state of the superconducting quantum bit by adopting a frequency division multiplexing mode. According to the embodiment of the invention, the hardware resource consumption of the quantum computer is reduced.

The invention relates to the technical field of power system simulation, and discloses a hardware-accelerated parallel multi-rate electromagnetic transient real-time simulation method of a converter. Initialized parametric constant admittance model modeling; step 2 realizes the cross-platform decoupling of the converter electrical system and control system solution process; step 3 pre-stores the converter model matrix in FPGA; step 4 is on the host computer Start the parallel simulation and predict the switch state at the next big step; step 5, the FPGA side analyzes the switching state calculation result of the host computer side and solves the electrical state at the current moment in parallel with step 4; step 6, the host computer side reads the FPGA side. The electrical state solves the results and updates the simulation time. The invention is applied to the FPGA-based hardware acceleration simulation scenario of the converter model, effectively reducing the error in the multi-rate decoupling calculation process of the control system and improving the accuracy of real-time simulation.

The invention discloses a high-energy-efficiency high-speed parallel LDPC encoding method and an encoder. The encoding method includes: dividing the input serial or parallel information sequence into multiple sections according to the size of the quasi-cyclic LDPC code cyclic shift sub-matrix, and converting It is an all-parallel data mode; cyclically shifts the segmented information sequence; selects the information bit at the corresponding position according to the position of the non-zero element in the first column of the cyclically shifted sub-matrix; merges the selected information bits of multiple segments; adopts In the pipeline processing mode, the merged information bits are accumulated by modulo two to obtain the corresponding parity bits; the serial parity bits are converted into a full parallel data mode; and the encoding result is output. According to the positions of the non-zero elements in the generating matrix, the present invention selects the bits of the information sequence first, and then performs the encoding calculation, which can effectively avoid the operation of invalid information bits, reduce the number of operations required for the encoding calculation, and thus significantly reduce the overall cost of the encoder. Hardware resource consumption.

The present invention provides a method and an apparatus for cell search and synchronization for subscriber stations of the Long Term Evolution (LTE) system. The invention uses primary synchronizing signal of primary synchronization code in each frame structure to establish synchronization with the base station when a subscriber station accesses the LTE network. With such synchronization between the subscriber station and the base station, control signals and transmission data may be correctly exchanged between them.