Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

DCT/IDCT multiplier circuit optimization method and application

A multiplier and circuit technology, applied in the field of digital video encoding and decoding, can solve the problems of high hardware overhead and high requirements for hardware connection design, and achieve the effect of reducing hardware resource consumption and improving computing efficiency.

Active Publication Date: 2020-01-31
MOLCHIP TECH (SHANGHAI) CO LTD
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

On the one hand, the related multiplication operations in the module also consume a lot of resources, resulting in a large corresponding hardware overhead
On the other hand, the butterfly algorithm in the algorithm causes a large amount of data transfer process, and also has high requirements for hardware connection design

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • DCT/IDCT multiplier circuit optimization method and application
  • DCT/IDCT multiplier circuit optimization method and application
  • DCT/IDCT multiplier circuit optimization method and application

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0058] For the relationship between the N×N signal matrix f and its N×N coefficient matrix F of the two-dimensional discrete cosine transform (DCT), it can be expressed by the following matrix multiplication:

[0059] f=C T ·F C ·C

[0060] f C =C f C T

[0061] Among them, C is the transformation matrix.

[0062] The multiplication of the matrix requires a large number of multipliers. The hardware basis of the multiplier is the adder structure, which is based on the algorithm of shift and addition. In a multiplier circuit, each bit of the multiplier is ANDed with each bit of the multiplicand to produce its corresponding product bit. These local products are shifted and fed into the array of full adders to obtain the multiplication results.

[0063] The transformation matrix C is a constant matrix, that is, the elements of the transformation matrix C are constants. In this embodiment, at first, the multipliers of the matrix are converted into a series of adders and subt...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a DCT / IDCT multiplier circuit optimization method and application, and relates to the technical field of digital video coding and decoding. A DCT / IDCT device used under an HEVCstandard comprises an optimization processing module which is used for collecting a row number contained in each type and elements in the corresponding set A according to the obtained information ofthe set A and the type N, enabling all elements in the set A corresponding to each type to serve as a group, and sequentially carrying out subtraction optimization and maximum correlation optimizationon the elements in the type, wherein maximum correlation optimization can take the process variables as related items when the process variables in a multiplication circuit can be used to reduce thetotal number of summators when any element in a group where the element is located is achieved when implementing judging of elements, and for all elements of each type, acquires the related item withthe highest occurrence frequency to serve as the maximum related item to achieve the related elements. According to the DCT / IDCT multiplier circuit optimization method, the hardware resource consumption is effectively reduced, and the operation efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of digital video coding and decoding. Background technique [0002] Video codec technology is the main technology for building and playing video, and the fundamental technology for all video applications. With the release of relevant national policies in the field of 4K ultra-clear TV, and the extensive application of AI in the field of video images. The rapid development of video image acquisition equipment, communication network and multimedia technology plays an increasingly important role in economy, security, scientific research and people's livelihood. At the same time, the ever-increasing video scale poses a huge challenge to the implementation of video coding and decoding technology. For example, the huge amount of video image data also brings many problems to storage and transmission. [0003] At present, a variety of video codec technology standards have been proposed internationally, such as M...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F17/14G06F17/16G06F7/52H04N19/625
CPCG06F7/52G06F17/147G06F17/16H04N19/625
Inventor 占坤张云韦虎雷理
Owner MOLCHIP TECH (SHANGHAI) CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products