Method and system for cipher card multi-algorithm parallel execution and relevant devices

Abstract

The invention discloses a method for cipher card multi-algorithm parallel execution. The method is applied to a PCI-E cipher card which is constituted based on an FPGA. The method comprises the stepsof setting a preset number of Function in an IP core according to the number of algorithms of the PCI-E cipher card, and configuring the same algorithm living example and configuration information forthe Function, so that an identification terminal identifies a preset number of PCI-E cipher cards; naming all Function named after corresponding function numbers according to a preset rule, and calling the Function corresponding to all the function numbers according to an instruction of a client layer API. A logic calculation resource can be more scientifically and reasonably utilized, the hardware resource utilization rate is higher, multiple algorithms at the same time or at the same time interval are all in the operation state, and the operation efficiency is obviously improved. The invention further discloses a system for cipher card multi-algorithm parallel execution, the PCI-E cipher card, and a computer readable storage medium, and the system for cipher card multi-algorithm parallel execution, the PCI-E cipher card, and the computer readable storage medium have the advantages.

Description

technical field [0001] The present application relates to the technical field of computer information security communication, and in particular to a method and system for parallel execution of multiple algorithms of an encryption card, a PCI-E encryption card, and a computer-readable storage medium. Background technique [0002] With the popularization of digital office, how to save the confidential data files generated in digital office is the focus of current research. There are mainly two ways of software encryption and hardware encryption. Encrypt confidential data files through a variety of encryption algorithms contained in the password card. [0003] The current encryption card interface protocol mainly adopts PCI (Peripheral Component Interconnect, peripheral component interconnection standard) and PCI-E (peripheral component interconnect express serial computer expansion bus standard). At present, high-end performance encryption cards mainly use FPGA ( Field-Progra...

AI Technical Summary

Problems solved by technology

[0003] The current encryption card interface protocol mainly adopts PCI (Peripheral Component Interconnect, peripheral component interconnection standard) and PCI-E (peripheral component interconnect express serial computer expansion bus standard). At present, high-end performance encryption cards mainly use FPGA ( Field-Programmable GateArray (Field Programmable Gate Array) platform PCI-E encryption card, and most of the PCI-E encryption cards on the market adopt the traditional operation process mode, that is, according to the write command, write data, wait for the result, return The steps are executed sequentially, and in order to ensure that the key data will not be rewritten or overwritten, the entire process generally adopts a locking mechanism, that is, it can only be executed in a single thread or serially between the sending of the write command and the return of the result. On the premise that the card supports multiple algorithms, there is still only one algorithm in the AND operation state at the same time or at the same time interval, which seriously wastes the logical computing resources provided by the inherent hardware and reduces computing efficiency.

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