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Binary FPRM circuit area and delay comprehensive optimization method

A technology of circuit area and optimization method, applied in multi-objective optimization, electrical digital data processing, special data processing applications, etc., can solve problems such as poor circuit optimization effect and premature convergence of algorithms

Active Publication Date: 2018-02-09
NINGBO UNIV
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

However, due to the strong pulling effect of the global optimal particle of the population, the algorithm tends to converge prematurely and fall into a local optimal solution, so that the optimal polarity searched by the algorithm is compared with the optimal polarity searched by the exhaustive method. , the circuit optimization effect will be poor

Method used

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  • Binary FPRM circuit area and delay comprehensive optimization method
  • Binary FPRM circuit area and delay comprehensive optimization method
  • Binary FPRM circuit area and delay comprehensive optimization method

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Embodiment

[0061] Embodiment: a kind of binary FPRM circuit area and time-delay comprehensive optimization method comprise the following steps:

[0062] ① Establish the area estimation model and delay estimation model of the binary FPRM circuit under p polarity:

[0063] ①-1 Express the binary FPRM circuit under p-polarity using the binary FPRM logic expression as:

[0064]

[0065] Among them, n is the function f p (x n-1 ,x n-2 ,...,x 0 ) the number of input variables; x n-1 ,x n-2 ,...,x 0 for the function f p (x n-1 ,x n-2 ,...,x 0 ) of n input variables, is the symbol of XOR operation, b j is the AND coefficient, and b j ∈{0,1}; j is the ordinal number of the AND item, and j is greater than or equal to 0 and less than or equal to 2 n An integer of -1, which can be expressed as j in binary n-1 j n-2 … j 0 ;p is the polarity of the binary FPRM circuit, which can be expressed as p in binary n-1 p n-2 …p 0 ; j is the AND expansion, expressed as i is an integer ...

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Abstract

The invention discloses a binary FPRM circuit area and delay comprehensive optimization method. The method comprises the steps of firstly building an area estimation model and a delay estimation modelof a binary FPRM circuit under p polarity, then associating optimal polarity search with particle swarm optimizing, searching the optimal polarity via a particle swarm, dividing the particle swarm into a first particle sub-swarm and a second particle sub-swarm during a sub-swarm optimizing process, and performing optimizing operation on the first particle sub-swarm and the second particle sub-swarm by using different learning strategies, wherein a mutual competition and learning relation exists between the first particle sub-swarm and the second particle sub-swarm. According to the method, diversity of optimizing is enhanced, during an optimizing process, a variation mechanism is introduced so that an algorithm is effectively prevented from running into the local optimization solution, and the optimizing capacity is improved; and the method has the advantages of good optimizing effect on the basis of relatively high optimizing efficiency.

Description

technical field [0001] The invention relates to an area and time delay comprehensive optimization method, in particular to a binary FPRM circuit area and time delay comprehensive optimization method. Background technique [0002] Boolean logic based on AND / OR / NOT operations and RM logic based on XOR / AND or XNOR / OR are two main manifestations of logic circuits. In the past, most integrated circuit optimization techniques based on Boolean logic have been established, and a set of systematic solutions has been established. However, a large number of studies have shown that circuits based on RM logic (such as arithmetic logic circuits, parity check circuits, etc.) have more obvious advantages than Boolean logic in terms of power consumption, area, speed, and testability. Therefore, the circuit area, delay and power consumption optimization techniques based on RM logic have received widespread attention. [0003] The fixed-polarity RM expansion is a common logical expansion in ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50G06N3/00
CPCG06F30/327G06F30/367G06F2111/06G06N3/006
Inventor 汪鹏君王铭波符强张会红
Owner NINGBO UNIV