Preparation method and structure of three-dimensional memory

Abstract

The invention provides a preparation method and a structure of a three-dimensional memory. According to the preparation method and the structure, a contact hole technology of a peripheral circuit region is advanced to be prior to a metal gate technology of an array memory region, so that etching of a contact hole to release of silicon oxide film stress of the peripheral circuit region is realized,distribution of macroscopic stress of a wafer is improved, and bending is effectively reduced. In addition, the contact hole technology of the peripheral circuit region is arranged prior to the metalgate technology of the array memory region, so that nonuniformity of local stress of the metal gate technology of the array memory region cannot cause contact failure of a peripheral circuit. The preparation method and the structure are realized by the following technical schemes.

Description

technical field [0001] The invention relates to the field of semiconductor devices and their manufacture, in particular to a preparation method and structure of a three-dimensional memory. Background technique [0002] With the continuous improvement of market demand for memory capacity, the number of memory cells that can be provided per unit area by traditional memory based on planar or two-dimensional structures is approaching the limit, which cannot further meet the market demand for larger capacity memory. Just like several bungalows built on a limited plane, these bungalows are neatly arranged, but as the demand continues to increase, the number of bungalows continues to blow out, but in the end this limited plane can only accommodate a certain number of bungalows. Cannot continue to increase. Planar memory is approaching its practical expansion limit, which brings severe challenges to the semiconductor memory industry. [0003] In order to solve the above difficulti...

AI Technical Summary

Problems solved by technology

Based on the existing manufacturing process of three-dimensional memory, when the number of stacked layers of memory cells increases, the thickness of the dielectric layer of the required peripheral circuit will increase. In the subsequent process, heat treatment makes the stress of the wafer uncontrollable. , the wafer becomes bent under the stress of thicker silicon dioxide. When the wafer is bent to a certain extent, it not only brings about the problem of overlay accuracy of the mask, but also affects the ability of the manipulator to grab the wafer; The three-dimensional memory chip is divided into an array storage area 12 and a peripheral circuit area 11. During the preparation of the array storage area 12, due to the inhomogeneity of local stress, the peripheral circuit area 11 is squeezed, so that when the contact hole 17 is formed, the contact Hole 17 cannot grow within the contact window of the device completely according to the design intention, resulting in contact failure

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