Soc (System-on-Chip) chip verification method

Abstract

The invention discloses an Soc (System-on-Chip) chip verification method. The method is characterized in that one or more that two bus address space segments are obtained by dividing in address spaceinside a to-be-verified Soc chip to use the same as a virtual communication interface, and a virtual interface including an external driving module and a monitoring module is also mounted outside theto-be-verified Soc chip; random-number application is monitored by the monitoring module, random data are generated through a random function, and the generated random data are written into a virtualstorage carrier through the external driving module; and different addresses are defined as different communication requests in an address range of the virtual communication interface, and whether a communication request belongs to the pre-planned communication requests is recognized by the virtual interface through address information of data on a bus. Generation of random excitation is effectively controlled through introducing real-time monitoring of the virtual communication interface, real-time interaction between a CPU program and a hardware simulation program is realized through information printing and simulation process control, quick locating of a problem is facilitated, and verification is enabled to quickly converge.

Description

technical field [0001] The invention relates to the field of Soc chip design and manufacture, in particular to a Soc chip verification method. Background technique [0002] With the continuous development of design and process technology, the scale of integrated circuit design is getting bigger and bigger, and the complexity is getting higher and higher. In order to shorten the time to market of chips and save development costs, the integration of multiple IPs has gradually become the mainstream, that is, SoC (System-on-Chip) technology is becoming more and more mature, but it also brings about an exponential increase in the complexity of SoC verification. Therefore, it is particularly important to have an efficient verification platform to quickly converge the verification. The convergence of verification is closely related to the effectiveness of incentive generation and the convenience of debugging, and CPUs are usually embedded in SoC chips, and the randomness of CPU pr...

AI Technical Summary

Problems solved by technology

Take the CPU program implemented in C language as an example. If the rand function is directly called in the C program to be random, since the rand function depends on the randomness of the seed, and the embedded CPU does not provide an effective seed generation mechanism, this will cause The data is fixed, that is, the SoC simulation runs a fixed test case every time, so the coverage cannot be improved.

Similarly, if an external program is used to generate random numbers and the C program include method, there is a disadvantage that the test case fails to run and the scenario cannot be reproduced

In addition, neither verification platform provides a good means of debugging, which greatly reduces the efficiency of locating problems

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