Semiconductor device and manufacturing method therefor and electronic apparatus

Abstract

The invention provides a semiconductor device and a manufacturing method therefor and an electronic apparatus, and relates to the technical field of a semiconductor. The manufacturing method comprisesthe steps of providing a semiconductor substrate, and forming a first fin structure, a second fin structure and a third fin structure in a pull-up transistor region, a pull-down transistor region anda transmission gate transistor region of the semiconductor substrate respectively; removing a first pseudo gate structure and a second pseudo gate structure to form a first gate groove and a second gate groove; forming a first P type work function layer at the bottom and on the side wall of the first gate groove in the pull-up transistor region; forming a second P type work function layer at thebottom and on the side wall of the first gate groove; forming a third P type work function layer at the bottoms and on the side walls of the first gate groove and the second gate groove in the pull-down transistor region; and forming an N type work function layer at the bottoms and on the side walls of the first gate groove and the second gate groove.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] In the field of semiconductor technology, static random access memory (SRAM) devices, as a typical semiconductor device, are widely used in electronic devices such as computers, mobile phones, and digital cameras. Currently, there are some designs that use fin field effect transistors (FinFETs) as transistor devices of SRAM cells to improve the density and performance of SRAMs. [0003] In order to adjust the α ratio, β ratio and γ ratio of the SRAM device to obtain better device performance, there is a method in the prior art: for the pull-up transistor (PU), pull-down transistor (PD) and pass-gate transistor of the SRAM device (PG) Select different numbers of fin structures, for example: 1, 1, 1, or 1, 2, 1, or 1, 3, 2 respectively. [0004] Different...

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Problems solved by technology

[0005] In FinFET devices, the work function layer is very important for the adjustment of the device. In the process of device preparation, the post metal gate process is usually used to form the work function layer. In order to meet the needs of the device, TiAlC needs to be used as the work function layer for NMOS, but at the boundary The diffusion of TiAlC is different, so the diffusion of Al can easily affect the mismatch performance of SRAM devices

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