Self-aligned top gate indium-tin-zinc oxide thin film transistor and manufacturing method thereof

Abstract

The invention discloses a self-aligned top gate indium-tin-zinc oxide thin film transistor and a manufacturing method thereof. The transistor comprises a substrate, a buffer layer, an indium-tin-zincoxide thin film, a gate dielectric layer, a conductive thin film, a passivation layer, a source-drain contact electrode and a gate electrode. By adopting a self-aligned top gate structure, the problems that a traditional bottom gate transistor is high in parasitic capacitance and low in scaling capacity are overcome; and different air sources and annealing conditions are utilized when the passivation layer and the gate dielectric layer are deposited, so that the indium-tin-zinc oxide thin film transistor is in contact with the gate dielectric layer and an indium-tin-zinc oxide thin film area covered with the indium-tin-zinc oxide thin film transistor is in a high resistance state, the indium-tin-zinc oxide thin film transistor is in contact with the passivation layer and the indium-tin-zinc oxide thin film area covered with the indium-tin-zinc oxide thin film transistor is in a low resistance state, thereby forming a high-resistance channel region and a low-resistance source-drain region and solving the problem of the thermal stability of a traditional ion-doped metal oxide thin film transistor. The self-aligned top gate indium-tin-zinc oxide thin film transistor can be widely applied to the field of semiconductors.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a self-aligned top gate indium tin zinc oxide thin film transistor and a manufacturing method thereof. Background technique [0002] Glossary: [0003] Precursor: It is the precursor or raw material for the synthesis of a substance. [0004] With the development and promotion of the next-generation new AMOLED active display, metal oxide thin film transistors have received more and more attention and research, among which bottom-gate indium tin zinc oxide thin film transistors (TFTs) are the most representative. However, the bottom-gate structure has the disadvantages of large parasitic capacitance and poor scaling capability, making it difficult to apply it to the integration of peripheral circuits to realize the system integration SOP of the display panel. A small number of scholars have carried out research on self-aligned top-gate structures with small parasitic capacitances. H...

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Problems solved by technology

However, the bottom-gate structure has the disadvantages of large parasitic capacitance and poor scaling capability, making it difficult to apply to the integration of peripheral circuits to realize the system integration SOP of the display panel.

A small number of scholars have carried out research on self-aligned top-gate structures with small parasitic capacitances. However, in the method of source-drain doping, hydrogen is generally used (J.Park et.al, Appl.Phys.Lett., 93, 053501 , 2008) or argon (B.DuAhn et.al, Appl.Phys.Lett., 93, 203506, 2008) plasma treatment to form a highly conductive region, since dopant ions easily diffuse from the source and drain regions to the channel, making The channel becomes low resistance, and the device is short-circuited. As long as a slight heat treatment is performed, the carrier concentration will change significantly, resulting in a sharp decline in device performance. Therefore, thin-film transistors that form high-conductivity regions by doping ions have thermal stability. Poor problem; and the formation of highly conductive regions by doping ions requires additional process steps, increasing production costs

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