A self-aligned top-gate indium tin zinc oxide thin film transistor and its manufacturing method

Abstract

The invention discloses a self-aligned top gate indium tin zinc oxide thin film transistor and a manufacturing method thereof. The transistor comprises a substrate, a buffer layer, an indium tin zinc oxide thin film, a gate dielectric layer, a conductive thin film, a passivation layer, a source drain contact electrode and gate electrode. The present invention adopts a self-aligned top-gate structure, which overcomes the problems of large parasitic capacitance and weak proportional reduction ability in traditional bottom-gate transistors, and uses different gas sources and annealing conditions when depositing passivation layers and depositing gate dielectric layers, so that The region of the indium tin zinc oxide film that is in contact with and covered by the gate dielectric layer presents a high resistance state, and the region of the indium tin zinc oxide film that is in contact with and covered by the passivation layer presents a low resistance state, thus forming a high resistance state. The channel region and the low-resistance source-drain region solve the thermal stability problem of the traditional metal oxide thin film transistor doped with ions. The invention can be widely used in the semiconductor field.

Description

Technical field [0001] The invention relates to the field of semiconductors, in particular to a self-aligned top gate indium tin zinc oxide thin film transistor and a manufacturing method thereof. Background technique [0002] Glossary: [0003] Precursor: It is the precursor or raw material for the synthesis of a substance. [0004] With the development and promotion of the next generation of new AMOLED active displays, metal oxide thin film transistors have received more and more attention and research, among which bottom gate indium tin zinc oxide thin film transistors (TFT) are the most representative. However, the bottom-gate structure has the shortcomings of large parasitic capacitance and poor scaling capability, so it is difficult to be applied to the integration of peripheral circuits to realize the system integration SOP of the display panel. A small number of scholars have carried out research on self-aligned top gate structures with small parasitic capacitance. However,...

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Problems solved by technology

However, the bottom-gate structure has the disadvantages of large parasitic capacitance and poor scaling capability, making it difficult to apply to the integration of peripheral circuits to realize the system integration SOP of the display panel.

A small number of scholars have carried out research on self-aligned top-gate structures with small parasitic capacitances. However, in the method of source-drain doping, hydrogen is generally used (J.Park et.al, Appl.Phys.Lett., 93, 053501 , 2008) or argon (B.DuAhn et.al, Appl.Phys.Lett., 93, 203506, 2008) plasma treatment to form a highly conductive region, since dopant ions easily diffuse from the source and drain regions to the channel, making The channel becomes low resistance, and the device is short-circuited. As long as a slight heat treatment is performed, the carrier concentration will change significantly, resulting in a sharp decline in device performance. Therefore, thin-film transistors that form high-conductivity regions by doping ions have thermal stability. Poor problem; and the formation of highly conductive regions by doping ions requires additional process steps, increasing production costs

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