Multi-rate compatible ldpc code encoder

An LDPC code and encoder technology, applied in coding, coding elements, error detection coding using multi-bit parity bits, etc., can solve the problems of large logic resource consumption and low RAM resource utilization, and reduce resource consumption. , The effect of saving FPGA logic resources and reducing the number of

Active Publication Date: 2020-12-15
10TH RES INST OF CETC
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  • Abstract
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  • Claims
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Problems solved by technology

[0004] The purpose of the present invention is aimed at the LDPC coder that the above-mentioned existing coding method can not dynamically reconfigure all code rates and information lengths stipulated by the CCSDS131. A realization method of 10 kinds of LDPC encoders stipulated in the 131.1-O-1 standard is proposed to save FPGA logic resources, improve the utilization rate of RAM resources, and be flexible and convenient.

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  • Multi-rate compatible ldpc code encoder
  • Multi-rate compatible ldpc code encoder

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Embodiment Construction

[0019] refer to figure 1 . In the embodiment described below, the multi-code-rate compatible LDPC encoder mainly includes: a main control logic module, a ping-pong DPRAM module, two groups of generating matrix group modules, a primitive single encoder module, a logic module controlled by a FIFO and a first-in-first-out FIFO output module composed of dequeue data buffer FIFO. The main control logic module receives the configuration parameters passed by the superior module, and provides timing control logic for the ping-pong DPRAM module, the generation matrix group module, the basic unit single encoder module, and the FIFO output module according to the configuration parameters; the generation matrix group module stores the standard data of the LDPC encoder The elements in the first row of the circulant matrix, the generator matrix is ​​composed of multiple quasi-circulant matrices, and it is used as the input signal of the basic unit single encoder module under the control of...

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Abstract

The invention provides a multi-bit-rate compatible LDPC code encoder. According to the multi-bit-rate compatible LDPC code encoder, the universality of the encoder is improved, the logic resources areremarkably reduced, and meanwhile, the utilization rate of the RAM resources is improved. The multi-bit-rate compatible LDPC code encoder is realized by the technical scheme as follows: a main control logic module receives configuration parameters transmitted by a superior module, and provides time sequence control logic for a ping-pong DPRAM module, a generated matrix storage module, an elementsingle encoder module and an FIFO output module according to the configuration parameters; meanwhile, the DPRAM ping-pong module sends cached data streams to be coded to a next-stage element single encoder module group for coding; the element single encoder adopts multiplication, addition and shift register operation, and dynamically reconstructs the logic length of the element single encoder to be a currently-implemented encoder quasi-cyclic matrix dimension according to the configuration parameters provided by the master control logic module; and finally, a FIFO control logic module outputscoded data to a rear stage according to judgment information bits provided by the main control logic module.

Description

technical field [0001] The invention relates to an LDPC code encoder which has been widely used in the fields of deep space communication, optical fiber communication, digital mobile communication and the like. Background technique [0002] Low-density parity-check code LDPC code has better performance than turbo code Turbo code, LDPC code has become one of the channel coding schemes in the fourth generation mobile communication (4G) system and the fifth generation mobile communication (5G) system . In the digital TV terrestrial broadcasting system, in order to meet different channel conditions and user needs of different receiving equipment, channel coding often needs to cooperate with multiple modulation methods. So that it can be flexibly applied in different occasions. This requires a certain flexibility in the width of the output code stream of the channel coding module of the communication system to provide the best code stream format for the coded symbol mapping mod...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
CPCH03M13/116
Inventor 张帆卢欧欣
Owner 10TH RES INST OF CETC
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