Communication system and communication method between multiple processors based on FPGA (Field Programmable Gate Array)

A communication system and processor technology, which is applied in the field of communication systems between multi-processors, can solve problems such as processor performance and cost waste, communication capacity limitations, processors that do not support Ethernet interfaces, etc., to reduce complexity, The effect of improving system stability

Inactive Publication Date: 2018-04-24
GUILIN UNIV OF ELECTRONIC TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] For the Ethernet interface communication mode, an additional Ethernet switch chip and peripheral circuits are required, and some processors with simple functions do not support the Ethernet interface; for dual-port RAM or RS232 communication mode, only two processors can be connected at the same time. Communication; for the SPI communication method, only one processor can be used as the master, and the rest of the processors can be used as slaves. The slaves can only receive communication requests, but cannot init...

Method used

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  • Communication system and communication method between multiple processors based on FPGA (Field Programmable Gate Array)
  • Communication system and communication method between multiple processors based on FPGA (Field Programmable Gate Array)
  • Communication system and communication method between multiple processors based on FPGA (Field Programmable Gate Array)

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Embodiment 1

[0042] In this embodiment, communication between two processors is taken as an example, wherein the communication interface of processor 1 is a parallel bus interface, and the communication interface of processor 2 is an Ethernet interface.

[0043] Firstly, the communication process in which processor 1 is the source processor and processor 2 is the destination processor is explained.

[0044] Step 1: Write communication commands

[0045] Processor 1 is interconnected with the interface unit through the parallel bus interface. Assuming that the data bus width in the parallel bus interface of processor 1 is 16 bits, that is, one write operation can write 2 bytes, then processor 1 divides a communication instruction into 4 write operations are written into the cache unit. After the interface unit detects the write operation of processor 1, it distinguishes which two bytes of the communication instruction the current write operation is based on the parallel bus interface address...

Embodiment 2

[0061] In this embodiment, communication between two processors is taken as an example, wherein the communication interface of processor 1 is an asynchronous RS232 interface, and the communication interface of processor 2 is an SPI interface.

[0062] First, the communication process in which processor 1 is the source processor and processor 2 is the destination processor is described.

[0063] Step 1: Write communication commands.

[0064] Processor 1 is interconnected with the interface unit through the asynchronous RS232 interface, refer to Image 6 It is the frame format of the asynchronous RS232 interface communication command. The frame starts with 0x55 bytes, followed by 8-byte communication commands, and ends with 0xAA bytes.

[0065] The processor 1 sends the communication instruction to the interface unit through the asynchronous RS232 interface according to the above frame format. The interface unit judges a complete frame according to the start identifier and the...

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Abstract

The invention discloses a communication system and a communication method between multiple processors based on an FPGA (Field Programmable Gate Array). The communication system comprises processors and an FPGA module connected with the processors; the FPGA module comprises interface units, cache units and a control unit which are sequentially connected with each other; the number of the interfaceunits and the number of the cache units are determined according to the number of processors needing to be communicated, wherein one end of each interface unit is connected with a communication interface of one processor, and used for sending and receiving a communication instruction by the processor; the other end of the interface unit is connected with the control unit through the cache units; and the control unit is used for transferring a communication instruction received by a cache unit of a source end processor to a cache unit of a destination end processor. The communication system ofthe invention can support different processors to realize mutual communication by adopting different communication interface types; the processors can all initiate communication requests without master slave restrictions; and for a system designed originally with an FPGA device, the complexity of a system circuit can be reduced and the system stability can be improved.

Description

technical field [0001] The invention relates to the field of communication and digital signal processing, in particular to a communication system and a communication method between FPGA-based multiprocessors. Background technique [0002] With the development of communication technology, the amount of data that processors need to process has increased sharply. A single processor can no longer meet the functional and performance requirements of the device. Multiple processors need to be integrated in a device or system, and each processor completes part Function, multi-processors work together to achieve the target function, therefore, the demand for mutual communication between the processors also increases. [0003] At present, the communication interfaces supported by the processor mainly include parallel bus interface, Ethernet interface, asynchronous RS232 interface and SPI interface. [0004] In order to realize the communication between multi-processors, it is often n...

Claims

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Application Information

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IPC IPC(8): G06F15/17G06F15/173
CPCG06F15/17G06F15/17306
Inventor 段筱雨周萍杜洋陈宏斌杨海燕展领
Owner GUILIN UNIV OF ELECTRONIC TECH
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