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Random clock generator

A random clock and generator technology, applied in random number generators, instruments, generation/distribution of signals, etc., can solve the problems of unpredictability of pure random clock generators, no random clock signals, slow clocks, etc.

Active Publication Date: 2018-05-11
THALES DIS FRANCE SA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the pseudo-random generator is still repetitive and therefore predictable after a certain period of time
[0005] The main disadvantage of a purely random clock generator is that it is too unpredictable and thus sometimes provides a clock that is too slow for the requested use
[0006] Currently, there is no ideal generator to provide a random clock signal

Method used

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Examples

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Embodiment Construction

[0017] figure 1 The clock generator circuit in corresponds to a preferred embodiment of the invention. According to a preferred embodiment, the clock generator operates in clock reduction mode and random clock generator mode while guaranteeing the average frequency. The clock generator circuit is preferably integrated in the same chip as the processor whose clocking is to be masked. In a preferred example, the master clock signal MClk is selected for use and converted into a converted clock signal SClk. This choice was made because it is possible and even recommended to use both the master clock MClk and the converted clock signal SClk on the integrated circuit in order to further mask the clocking by the converted clock signal SClk. In this way, the generation of the master clock signal MClk is not shown, but it can be obtained by any type of oscillator circuit known to a person skilled in the art. As an example, it would be appropriate to introduce a ring oscillator on th...

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PUM

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Abstract

The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output signal corresponding to a train of N pulses every M clock pulse, M being a whole number higher than 1 and N being a whole number higher than 1 and lower than or equal to M. A number generator (102) and (103) supplies a new number (N) to the clock signal reduction circuit every P pulse of a master clock signal, N and / or P being produced randomly.

Description

technical field [0001] The present invention relates to random clock signal generators. This type of generator is used in clock processors where synchronization with external devices is to be avoided. Background technique [0002] To ensure a certain level of security in communications and electronic transactions, encrypted information exchanges are sometimes used. In order to guarantee the confidentiality of the keys used, it is common to use secure integrated circuits commonly known as secure elements or SEs. SEs are commonly used in chip cards, USB keys or other secure portable devices, or even integrated in larger devices such as computers or mobile phones. [0003] These SEs have a number of security elements in order to protect the confidentiality of the information they contain. To this end, attacks that could be used to extract confidential information are sometimes identified, and countermeasures are sometimes integrated in the SE against each type of attack. Am...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/58H03K3/84G06F1/04
CPCG06F7/588H03K3/84G06F1/08G06F21/725G06F1/04G06F1/06
Inventor P.劳贝特蒙迪J-R.库隆J.E.佩雷斯查莫罗
Owner THALES DIS FRANCE SA
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