FPGA aging test system and circuit configuration method thereof

Abstract

The invention discloses an FPGA aging test system and a circuit configuration method thereof. The FPGA aging test system comprises multiple aging boards, a power distribution board and a configurationand monitoring board, wherein the multiple aging boards are placed in an aging temperature box, each aging board comprises a plurality of FPGA chip sockets, a power supply interface and a crystal vibrator, and excitation is provided for the aging board; the power distribution board is placed outside the aging temperature box and provides multi-way independent power for each aging board; and the configuration and monitoring board is arranged outside the aging temperature box and comprises a PROM configuration chip. In the aging test, a plurality of different FPGA chips are placed in the FPGA chip sockets in the aging board and through the PROM configuration chip of the configuration and monitoring board, one PROM is controlled to simultaneously configure the plurality of different FPGA chips in a passive serial mode. The system is applicable to different FPGA chips with the same packaging, universality is realized, the number of required nonvolatile storage devices is saved, and through introducing a state monitoring system and safety assurance measures, the chip state during the aging process can be monitored in real time.

Description

technical field [0001] The disclosure belongs to the technical field of integrated circuits, and relates to an FPGA burn-in test system and a circuit configuration method thereof. Background technique [0002] FPGA has the advantages of programmable, high integration, high speed and high reliability. By configuring the logic functions and input / output ports inside the device, the original circuit board-level design is placed in the chip, which improves circuit performance, reduces circuit volume, reduces circuit power consumption, and effectively improves design flexibility. and efficiency. [0003] At present, integrated circuits have been widely used in aviation, military, industrial and other industries, and their reliability has become a major consideration for the wide application of devices. As one of the most important reliability tests, burn-in test is a method to make products A method of working under stress for a period of time to stabilize its properties. The ...

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Problems solved by technology

[0004] The burn-in test for FPGA has become an optional reliability test to ensure the pass rate of FPGA. Compared with other monolithic integrated circuits, FPGA is volatile and requires special non-volatile devices to store configuration information. FPGA It needs to be configured before working, and the function will be lost after the chip is powered off

[0005] Based on the wide application of FPGA, there are various test systems and methods for burn-in tests on various FPGA devices. Different test systems and methods may be poorly compatible, cumbersome and time-consuming, so it is urgent It is necessary to propose a general-purpose FPGA burn-in test system with a simple structure and suitable for process-based mass production

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