A method of matrix transposition based on sdram chip

Abstract

The invention discloses a matrix transposition method based on an SDRAM chip, and provides a reading address and writing address generation method according with SDRAM chip device characteristics. Formatrix transposition application of adopting the SDRAM chip as a large-capacity storage device, the matrix transposition method is simple in principles and easy to realize, seamless butt-joint connection can be realized in continuous data input / output without the need for a refreshing operation, and transposition efficiency can reach 100%.

Description

technical field [0001] The invention relates to a matrix transposition method based on an SDRAM chip, belonging to the technical field of matrix data processing. Background technique [0002] Matrix transposition is a commonly used process in multidimensional image and signal processing. Matrix transposition can be regarded as a mapping between two matrices: X i,j →X j,i . When the application scale is relatively small, the entire matrix can be read into the high-speed memory at one time, and the matrix transposition is very simple. For large-scale applications, the high-speed memory capacity is not enough, and a large amount of data must be stored in an external memory, so transposition efficiency is very important in the entire processing process. [0003] Synchronous dynamic random access memory (hereinafter referred to as SDRAM) chip is one of the most widely used memories due to its advantages of large storage capacity, high speed and low power consumption. Common S...

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Problems solved by technology

There are many articles using the matrix block transposition method, all of which divide the original matrix into multiple sub-matrices to increase the number of consecutive accesses after each activation in discrete operations, so as to reduce SDRAM chip activation and precharge operations. times, so as to reduce the impact of SDRAM chip control commands on access efficiency, but their transposition efficiency will be more or less affected by the overhead of SDRAM chip control commands

[0004] Whether it is a two-page, three-page or matrix block type, these methods are very effective in data input and output balance transposition. Operations such as writing and refreshing will generate additional control command overhead. These methods fail to make full use of the characteristics of the SDRAM chip device, which affects the transposition efficiency and cannot be optimized.

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