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Loading method and device of FPGA program data

A technology of program data and sub-data, applied in the computer field, can solve the problem of time-consuming and achieve the effect of reducing time

Active Publication Date: 2018-06-08
HANGZHOU DPTECH TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When debugging the function of the program data of the FPGA, it is necessary to replace the program data of the FPGA repeatedly, and it takes too much time to disassemble the flash chip from the network device and erase the program data every time.

Method used

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  • Loading method and device of FPGA program data
  • Loading method and device of FPGA program data
  • Loading method and device of FPGA program data

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Embodiment Construction

[0070] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, and to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, the following describes the existing technical solutions and the present invention in conjunction with the accompanying drawings. The technical solutions in the embodiments of the invention are described in further detail.

[0071] see figure 2 , is an architectural diagram of a network device shown in this application, such as figure 2 As shown, the network device includes CPU, memory, version control FPGA and business processing FPGA; wherein, the version control FPGA is used to load program data for the business processing FPGA, and its function is similar to that of the CPLD in the background technology. The memory of a network device is divided into a user state space and a kernel state spa...

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Abstract

The invention provides a loading method and device for FPGA program data, and the method and the device are applied to a network device. The method includes the following steps that the program data is obtained from a specified location of an external device, and the program data is stored to a user state space; the program data is copied to a program data cache region of a kernel state space; a loading command is sent to a version control FPGA, and the version control FPGA loads the program data from the program data cache region to a business processing FPGA. According to the technical scheme, the situation that flash chips are repeatedly dismantled in the FPGA program data loading process and the program data is repeatedly erased or written on the flash chips is avoided, and the time for loading the FPGA program data is significantly reduced.

Description

technical field [0001] The present application relates to the field of computer technology, in particular to a method and device for loading FPGA program data. Background technique [0002] FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) is programmed based on SRAM (Static Random Access Memory, Static Random Access Memory), and the program data of FPGA stored on SRAM will be lost when the system is powered off. Wherein, the program data includes program software running on the FPGA. Every time the system is powered on, the CPU (Central Processing Unit, central processing unit) needs to rewrite the program data stored in the memory chip outside the FPGA into the SRAM inside the FPGA. Wherein, the memory chip includes EEPROM (Electrically Erasable Programmable read only memory, electrically erasable read only memory) and flash chip (Flash EEPROM Memory). [0003] see figure 1 , is an architecture diagram of a network device in the prior art, such as fig...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/445
CPCG06F9/44521
Inventor 项东阳
Owner HANGZHOU DPTECH TECH
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