DMA broadcast data transmission method based on host count in GPDSP

Abstract

The invention discloses a DMA broadcast data transmission method based on host count in GPDSP. The method comprises the following steps: a host DMA starts DMA broadcast data transmission to generate abroadcast read request, wherein the broadcast read request is sent to the off-core through an on-chip network; the host DMA receives read return data from each slave DMA, and counts the same to confirm whether the data transmission is finished; the host DMA sends a cache clearing command to all slave DMAs when confirming that the data transmission is finished, and each slave DMA ends the broadcast transmission after receiving the cache clearing command and executing the cache clearing operation. The DMA broadcast data transmission is realized by starting once DMA transmission affair, and themethod has the advantages of being simple in principle, low in cost, small in DMA transmission power consumption and starting expenditure, high in data transmission efficiency and DDR read efficiency,and large in transmission bandwidth.

Description

technical field [0001] The invention relates to the technical field of GPDSP (General Purpose Digital Signal Processor, general purpose digital signal processor), in particular to a DMA (Director Memory Access, direct storage access) broadcast data transmission method based on host counting in GPDSP. Background technique [0002] GPDSP is a new architecture that not only maintains the basic characteristics of embedded DSP and the advantages of high performance and low power consumption, but also can efficiently support general scientific computing. Efficient support for 64-bit high-performance computers and embedded high-precision signal processing. The structure has the following characteristics: ①It has direct representation of double-precision floating point and 64-bit vertex data, general-purpose registers, data buses, and instruction bits are more than 64 bits wide, and the address bus is more than 40 bits; ②CPU and DSP heterogeneous multi-core are tightly coupled, CPU ...

AI Technical Summary

Problems solved by technology

Since the DMA technology overlaps the calculation operation of the core and the data movement operation of the storage unit, it reduces the impact of the data transmission speed between the internal storage unit and the external storage unit on the GPDSP processing performance to a certain extent.

However, as the number of processing cores integrated in GPDSP continues to increase, the existing DMA data transmission methods can no longer meet the data volume requirements of multi-core parallel processing. Efficient multi-core DMA involves the memory access requirements of applications and the hardware structure of multi-core GPDSP. characteristic

[0005] When common algorithms and applications such as matrix multiplication, fast Fourier transform, and HPL (High Performance Linpack) are implemented in parallel on multi-core GPDSP, all cores may access the same storage space for a period of time, such as GEMM matrix multiplication operations (C+=AB), the A matrix is ​​a shared matrix, and all DSP cores need matrix A; if the traditional DMA transmission method is used, each DSP core initiates a point-to-point transmission to read the data block on the same position of the DDR. Because the distance between each core and DDR is different, the data read by different cores may be on different DDR pages, which will lead to the loss of DDR page hits, increase the number of DDR page changes, and increase the memory access delay. , which greatly reduces the read efficiency of DDR; if there are multiple or all cores to start DMA transfer transactions, it will not only cause a lot of power consumption, but also cause pressure on the network, and there will be competition or hits when accessing the DDR storage space outside the core Lost etc.

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