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Method for testing bridging in adjacent semiconductor devices and test structure

A semiconductor and device technology, applied in the field of test structure, can solve problems such as short circuit and poor device yield

Active Publication Date: 2018-07-10
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] During semiconductor device fabrication, improper alignment of components on a semiconductor device can lead to short circuits and poor device yield

Method used

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  • Method for testing bridging in adjacent semiconductor devices and test structure
  • Method for testing bridging in adjacent semiconductor devices and test structure
  • Method for testing bridging in adjacent semiconductor devices and test structure

Examples

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Embodiment Construction

[0025] The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to limit the invention. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on process conditions and / or desired performance of the device. In addition, in the following description, forming a first component on or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component. components so that the first component and the second component may not be in direct contact with each other. Various features may be arbitrarily drawn i...

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Abstract

A method for testing bridging between adjacent semiconductor devices includes forming a patterned diffusion region on a semiconductor substrate, and forming a first conductive layer over the diffusionregion. The first conductive layer is patterned in a same pattern as the patterned diffusion region. An exposed portion of the first conductive layer is removed to expose a portion of the diffusion region. A source / drain region is formed over the exposed portion of the diffusion region, and a dielectric layer is formed over the source / drain region. A third conductive layer is formed over the dielectric layer. End portions of a second conductive layer are removed along the first direction to expose first and second end portions of the first conductive layer. Electrical resistance across the first conductive layer between the first and second end portions of the first conductive layer is measured. Embodiments of the invention also relate to a test structure.

Description

technical field [0001] Embodiments of the present invention are directed to methods for testing semiconductor devices and structures for testing. In particular, the invention is directed to testing devices on semiconductor substrates. Background technique [0002] During semiconductor device fabrication, improper alignment of components on a semiconductor device can lead to short circuits and poor device yield. Testing of the alignment of device components on semiconductor wafers is desirable to avoid additional processing steps for defective devices. Contents of the invention [0003] An embodiment of the present invention provides a method for testing a bridge between adjacent semiconductor devices, comprising: forming a patterned diffusion region on a semiconductor substrate; forming a first conductive layer over the diffusion region, wherein , patterning the first conductive layer into the same pattern as the patterned diffusion region; forming a second conductive la...

Claims

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Application Information

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IPC IPC(8): H01L21/66
CPCH01L22/34H01L29/42328H01L29/40114H10B41/00H10B41/42H10B41/30H01L22/14H01L21/311H01L21/3213H01L22/10G01R31/2812H01L22/20
Inventor 林孟汉梁佳琳谢智仁
Owner TAIWAN SEMICON MFG CO LTD