Sampling time mismatch calibration device and method, and time interleaving analog-to-digital converter

A sampling time and calibration device technology, applied in analog-to-digital converters, analog-to-digital conversion, code conversion, etc., can solve problems such as unable to calibrate normally, achieve fast calibration speed, and expand the effect of applicable occasions

Active Publication Date: 2018-07-13
SHANGHAI BEILING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is to overcome the inherent defects of the calibration system structure in the prior art, which cannot be calibrated normally when the signal frequency is coherent with the sampling clock frequency, and provide a sampling time mismatch calibration device, method and time Interleaved ADC

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  • Sampling time mismatch calibration device and method, and time interleaving analog-to-digital converter
  • Sampling time mismatch calibration device and method, and time interleaving analog-to-digital converter
  • Sampling time mismatch calibration device and method, and time interleaving analog-to-digital converter

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Embodiment 1

[0039] like Figure 5 As shown, the sampling time mismatch calibration device involved in this embodiment includes a reference channel 1, several sampling sub-channels 2 (only one sampling sub-channel 2 is shown in the figure for simplicity of illustration) and a calibration adjustment module 3, the reference channel 1. The sampling sub-channels 2 are electrically connected to the calibration adjustment module 3. The sampling time mismatch calibration device also includes a pseudo-random level generator 4, which is connected to the reference channel 1 and the sampling sub-channel 2 respectively. Electrically connected, the pseudo-random level generator 4 is used to generate the pseudo-random level Vth corresponding to each reference clock phi_cal, and the reference channel 1 is used to control the received analog signal Vin and the pseudo-random level under the control of the reference clock phi_cal Vth is sampled, and the first polarity signal D is output to the calibration a...

Embodiment 2

[0047] like Figure 7 As shown, the sampling time mismatch calibration device involved in this embodiment is based on the embodiment 1. During specific implementation, the reference channel 1 adopts the circuit form of a comparator to realize the function described in the embodiment 1, that is, the reference Channel 1 includes the first comparator A1, the positive input terminal of the first comparator A1 receives the analog signal Vin, the negative input terminal of the first comparator A1 receives the pseudo-random level Vth, the output terminal of the first comparator A1 is connected with the calibration adjustment Module 3 is electrically connected, and the first comparator A1 outputs the first polarity signal D under the control of the reference clock phi_cal 1 . By using a simple circuit form such as a comparator, the function of reference channel 1 can be realized, which not only eliminates the influence of ADC quantization error on calibration, that is, calibration is...

Embodiment 3

[0052] like Figure 8 As shown, the sampling time mismatch calibration method involved in this embodiment includes:

[0053] Step 101, the pseudo-random level generator generates a pseudo-random level corresponding to each reference clock;

[0054] Step 102, the reference channel samples the received analog signal and the pseudo-random level respectively under the control of the reference clock, and outputs the first polarity signal after comparing the sampling results;

[0055] Step 103, the sampling sub-channel samples the received analog signal and the pseudo-random level respectively under the control of the sub-sampling clock, and outputs a second polarity signal after comparing the sampling results;

[0056] Step 104, the calibration adjustment module counts the number of zero-crossing points between the sampling sub-channel and the reference channel within a period of time according to the first polarity signal and the second polarity signal, and adjusts the The amoun...

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Abstract

The invention discloses a sampling time mismatch calibration device and method, and a time interleaving analog-to-digital converter. The sampling time mismatch calibration device comprises a referencechannel, a plurality of sampling sub-channels, a calibration adjustment module and a pseudo random level generator, the reference channel and the sampling sub-channels are electrically connected withthe calibration adjustment module, and the pseudo random level generator is electrically connected with the reference channel and the sampling sub-channels respectively. The sampling time mismatch calibration device disclosed by the invention adopts the pseudo random level generator, obtains the polarity of a sampling point of the reference channel and the polarity of the sampling points of the sampling sub-channels according to a pseudo random level Vth, then obtains the number of zero-crossing points by simple polarity statistics, and then adjusts the delay value of a sub-sampling clock relative to a reference clock according to the number of zero-crossing points so as to achieve calibration, the calibration speed is high, and the sampling time mismatch calibration device is not limitedby the number of channels, and can also be applied to coherent sampling.

Description

technical field [0001] The invention relates to the technical field of analog-to-digital conversion, in particular to a sampling time mismatch calibration device and method, and a time-interleaved analog-to-digital converter. Background technique [0002] In a traditional multi-channel TIADC (Time interleaved analog-to-digital converter, time interleaved analog-to-digital converter), the sampling time calibration of the sampling sub-ADC channel is generally performed through an additional calibration ADC channel. [0003] figure 1 It is a block diagram of a calibration system based on cross-correlation statistics. When the sampling time mismatch between the sampling signal phi_cal of the calibration ADC channel (Cal-ADC) and the sampling signal phi_sub of the sampling sub-ADC channel (Sub-ADC) is smaller, the two channels The greater the correlation of the sampling output Dout of the input signal Vin, the cross-correlation after mutual calculation and cumulative average w...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10H03M1/12
CPCH03M1/1009H03M1/121H03M1/1245
Inventor 富浩宇张辉李丹王海军陈正李琪林高远
Owner SHANGHAI BEILING
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