Method for constructing symbol synchronization circuit in GFSK receiver

Abstract

The invention provides a method for constructing a symbol synchronization circuit in a GFSK receiver. The method comprises the following steps: step (1) after a DC component is removed from a phase signal, performing interpolation calculation; step (2): performing timing error information detection based on the interpolation calculation; step (3): feeding back the detected timing error informationto an interpolation filter for interpolation; and step (4): continuously adjusting, by the interpolation filter, a sampled clock to complete the synchronization of symbol clocks of sending and receiving ends in the GFSK receiver. According to the method, differential phase discrimination processing is performed on the baseband signal at first, and then the baseband signal is used as the input ofthe symbol synchronization circuit after frame synchronization and the frequency offset compensation with the removed DC component. The timing error is fed back to the interpolation filter through theloop filter, and the new sample value is continuously adjusted, and finally the sampling clock of the interpolator converges to the symbol clock, thereby synchronizing the symbols of the transmittingend and the receiving end.

Description

technical field [0001] The invention relates to the field of fast symbol synchronization in a GFSK receiver, in particular to a construction method of a symbol synchronization circuit in the GFSK receiver. Background technique [0002] Signals received by wireless digital receivers often have symbol timing deviations during communication. Therefore, it is necessary to restore the best sampling point through a symbol synchronization circuit. The all-digital receiver adopts a fixed sampling frequency, the sampling clock and the symbol clock are independent of each other, and the timing error obtained by the timing synchronization circuit is used to control the interpolation filter to output the best sampling point of the symbol. [0003] Generally speaking, the symbol synchronization circuit is composed of four parts including interpolation filter (Interpolator), timing error detector (CTimingError Detector), loop filter (LPF) and numerically controlled oscillator (NC0). [...

AI Technical Summary

Problems solved by technology

However, since the accuracy of the clocks at the transmitter and receiver is inevitably affected by temperature drift, in practical applications, the best sampling point obtained by frame synchronization cannot always be aligned with the middle of the symbol period. With the sampling clock error The accumulation of will lead to the degradation of receiver demodulation performance

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