Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures

Abstract

Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal Hues using individual drivers, A driver of the individual drivers is configured to drive more than two voltages.

Description

Background technique [0001] The quest to make computing systems more powerful and more power efficient has brought about advances in interface communications that improve throughput without increasing, and ideally reducing, energy consumption. In general, as clock speeds increase, it is desirable to increase data transition times on the interface bus to match the faster clock speeds. Future double data rate (DDR) dynamic random access memory (DRAM) performance targets will soon exceed DRAM transistor switching capabilities. Some systems have implemented data encoding and specialized multi-level (eg, more than two levels) bus architectures to increase the throughput achieved over the interface bus. However, these specialized architectures add cost and complexity and require additional input / output (I / O) pins. Contents of the invention [0002] Apparatus and methods for multi-level communication architectures are disclosed herein, for example, apparatus and methods for encod...

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Problems solved by technology

However, these specialized architectures add cost and complexity and require additional input / output (I / O) pins

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