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Novel slew rate enhancement circuit and low dropout regulator

A new type of slew rate enhancement technology, which is applied in the direction of instruments, electric variable adjustment, control/regulation system, etc., can solve the problems of increased power consumption, larger LDO layout area, etc., to reduce quiescent current, improve slew rate limit, Effect of Slew Rate Limiting Improvement

Inactive Publication Date: 2018-09-07
SHENZHEN UNIV
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  • Claims
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AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a novel slew rate enhancement circuit and a low-dropout linear regulator, aiming at improving the transient characteristics by adopting an off-chip capacitor and increasing the quiescent current in the prior art, which makes the LDO layout area Problems of increased size and increased power consumption

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  • Novel slew rate enhancement circuit and low dropout regulator
  • Novel slew rate enhancement circuit and low dropout regulator
  • Novel slew rate enhancement circuit and low dropout regulator

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Embodiment Construction

[0022] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0023] LDO considers its transient characteristics through its load current. When the load current changes from large to small, the gate of the power regulator cannot quickly respond to its voltage change, and the output voltage VDDL will form an overshoot, and return to the normal value after a certain period of time. ; Similarly, when the load current changes from small to large, the gate voltage of the power regulator cannot quickly respond to its voltage change, and most of the load current can only be provided by the load capacitor, which causes the output voltage VDDL to form an undershoot unt...

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Abstract

The invention is applicable to circuit design, and provides a novel slew rate enhancement circuit comprising a plurality of MOS tubes and a plurality of capacitors; the plurality of capacitors are used for detecting the change of feedback voltage input from the outside, and sending a control signal to the plurality of MOS tubes when detecting that the feedback voltage changes; the plurality of MOStubes are used for controlling rising or reduction of voltage output from the output terminal of the novel slew rate enhancement circuit according to the control signal, so that limitation of the slew rate of a power regulation tube connected with the output terminal of the novel slew rate enhancement circuit is improved. The novel slew rate enhancement circuit provided by the embodiment of the invention can improve the limitation of the slew rate of the power regulating tube at the moment of load jumping change, so as to improve the integral instant response and reduce quiescent current. When load current generates transient change or generates switching rag and peak, change of output voltage can be rapidly detected by the feedback voltage, and charging and discharging can be performed on the grid capacitance and Maitreya equivalent capacitance of the power regulating tube, and finally the transient characteristic of the circuit is greatly improved.

Description

technical field [0001] The invention belongs to circuit design, in particular to a novel slew rate enhancing circuit and a low-dropout linear regulator. Background technique [0002] With the development of people's living standards, all kinds of portable electronic devices, such as mobile phones and tablet computers, are increasingly inseparable from life. Such portable devices usually use 5V or 12V power supply, but the internal power supply of the chip is usually below 3V, while low-voltage The differential linear regulator LDO (Low Dropout Regulator) is the best choice for this kind of step-down conversion, and the related circuits of LDO have become a very important type of circuit in power management chips. LDO has the advantages of simple structure, low cost, small chip area, and low static power consumption. [0003] Traditional LDO related circuits such as figure 1 , because most of the chips on the market use digital-analog hybrid circuits. When the chip is work...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05F1/56
CPCG05F1/561
Inventor 姜梅孙凯张瀚元阳召成
Owner SHENZHEN UNIV
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