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A delay-locked loop with automatic precision adjustment and its adjustment method

A delay-locked loop, automatic adjustment technology, applied in the direction of automatic power control, electrical components, etc., can solve the problem of DLL can not work, to achieve the effect of ensuring the reliability of work

Active Publication Date: 2021-11-19
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The precision of the DLL's phase detection module is determined by the DLL's delay unit and the precision requirements of the entire DLL. Sometimes it is difficult for the two to match normally and the DLL cannot work.

Method used

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  • A delay-locked loop with automatic precision adjustment and its adjustment method
  • A delay-locked loop with automatic precision adjustment and its adjustment method
  • A delay-locked loop with automatic precision adjustment and its adjustment method

Examples

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Embodiment 1

[0045] as attached figure 2 As shown, in this embodiment, we take the control module to output four control words. In this embodiment, we use Ci[m:0] to represent the binary representation corresponding to Ci, and m+1 represents the binary representation corresponding to Ci The number of digits, when i-4, this embodiment takes m=7. The clocks corresponding to the delay time from large to small are CLK_OUT[4], CLK_OUT[3], CLK_OUT[2] and CLK_OUT[1], and the control words corresponding to these 4 clocks are C4[7:0], C3[ 7:0], C2[7:0] and C1[7:0], then CLK[4] is the feedback clock CLK_FB.

[0046] Among them, C4[7:0], C3[7:0], C2[7:0] and C1[7:0] always maintain the following relationship:

[0047] C1[7:0]=C4[7:0] / 4;

[0048] C2[7:0]=(2*C4[7:0]) / 4;

[0049] C2[7:0]=(3*C4[7:0]) / 4.

[0050] The input and output of the selection module always maintain the following relationship:

[0051] CLK_OUT[4]=CLK_D[a4];

[0052] CLK_OUT[3]=CLK_D[a3];

[0053] CLK_OUT[2]=CLK_D[a2];

[...

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Abstract

The invention discloses a delay phase-locked loop with automatic precision adjustment, which includes a phase detection module, a delay module, a control module and a selection module; the two input ports of the phase detection module are respectively connected to a reference clock and a feedback clock, and the phase state output The port is connected to the input port of the control module; the output port of the control module is connected to the input port I of the selection module; the input port of the delay module is connected to the reference clock, and the output port of the delay module is connected to the The input port II of the selection module; the output port of the selection module outputs the selected clock; wherein, the phase detection module includes a phase detection unit, a storage unit, a judgment unit and a phase control unit. The delay phase-locked loop with automatic precision adjustment provided by the present invention repeatedly adjusts the precision of the phase detection module to make the DLL work at the minimum precision and ensure the reliability of the DLL.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a delay phase-locked loop with automatic precision adjustment and an adjustment method thereof. Background technique [0002] With the development of CMOS integrated circuit technology, clock circuits play a very important role in both digital and analog integrated circuit design. However, PLL (Phasel Locked Loop) phase-locked loops are basically designed using analog circuits, and the circuit noise problem is relatively large, and the circuit design is difficult and the reusability is poor. The DLL (Delay Locked Loop) delay-locked loop, especially the all-digital DLL circuit, is more and more widely used because it is completed based on digital logic, the circuit noise performance is good, and the circuit has strong reusability. [0003] Moreover, in some circuit designs, not only strict requirements are placed on the clock frequency, but also the phase of the clock is also v...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/081H03L7/085
CPCH03L7/0812H03L7/085
Inventor 曾夕董林妹袁庆严慧婕李志芳
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT