Clock frequency dividing circuit and frequency dividing method thereof

Abstract

The invention discloses a clock frequency dividing circuit and a frequency dividing method thereof. The clock frequency dividing circuit comprises a counter, a first latch, a second latch, a phase inverter, a synchronizer and an AND gate, wherein an output end of the counter is connected with an input end of the first latch; an output end of the first latch is connected with an input end of the AND gate; an output end of the counter is connected with an input end of the synchronizer; an output end of the synchronizer is connected with an input end of the second latch; an output end of the second latch is connected with the input end of the AND gate; an output end of the phase inverter is connected with an input end of the second latch; an external input signal is input into the counter, the first latch and the phase inverter as a clock source clock. Through adoption of a two third clock frequency dividing circuit and the frequency dividing method, power consumption and performance balance of a chip can be realized better; accurate two third frequency dividing timing can be realized; and more frequency options can be realized for a chip system.

Description

technical field [0001] The present invention relates to the technical field of integrated circuit design, in particular to a clock frequency division circuit and a frequency division method thereof. Background technique [0002] Existing even clock frequency division (2, 4 frequency division) circuit structure, such as figure 1 As shown, the even clock frequency division circuit is composed of a counter, an inverter and a flip-flop to complete the frequency division function of the clock. The working principle of the existing even-numbered clock frequency division circuit is to use the input clock source clock signal as a counting pulse. Since the output terminal of the counter outputs pulses according to a certain rule, the signal pulses output from different ports can be regarded as It is the "frequency division" of the input signal, and the working process of the frequency division frequency is determined by the selected counter. Therefore, if the binary counter is selec...

AI Technical Summary

Problems solved by technology

However, after the chip adopts the existing even clock frequency division circuit and its frequency division method, although the power consumption of the chip is doubled, its operation speed will also be doubled, resulting in the inability to have both power consumption and speed of the chip , can not meet the design requirements

Images