Task mapping method for information security of multi-core processor

A multi-core processor, task mapping technology, applied in the fields of electrical digital data processing, computer security devices, instruments, etc., can solve the problem of reducing the success rate, hot side channel leakage, reducing command information and the correlation between transient temperature and space temperature, etc. problems, to achieve the effect of reducing the success rate and reducing the relevance

Active Publication Date: 2018-09-21
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology

[0007] The purpose of the present invention is to address the problem of hot side channel leakage of multi-processors on a chip, and propose a task mapping method for information security of multi-core processors, so as to reduce the difference between the instruction information of the processor and the transient temperature and the space temperature during execution. Correlation between the chips, thereby reducing the success rate of attackers using hot side channels to steal information from chips

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  • Task mapping method for information security of multi-core processor
  • Task mapping method for information security of multi-core processor
  • Task mapping method for information security of multi-core processor

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[0046] Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the implementations shown and described in the drawings are only exemplary, intended to explain the principle and spirit of the present invention, rather than limit the scope of the present invention.

[0047] The embodiment of the present invention provides a task mapping method for multi-core processor information security, such as figure 1 As shown, including the following steps S1-S9:

[0048] S1. Obtain the number n of processor cores and the number m of threads included in the task.

[0049] S2. Judging whether n

[0050] S3. Calculate and obtain a weight matrix W according to the location information of each processor core.

[0051] The i-th element of the weight matrix W is the weight value W of processor i (xi,yi)...

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Abstract

The invention discloses a task mapping method for the information security of a multi-core processor, and belongs to the technical field of on-chip multi-processor task mapping algorithm and hardwaresecurity. For the hot side information channel leakage problem of the multi-core processor, the dynamic security task mapping method is provided, a task thread is mapped to the optimum combination selected from a processor core set with the same cost function value, the correlation between the instruction information of the processor in the executing process and the transient temperature and spacetemperature is reduced, and therefore the success rate of stealing information on a chip through a hot side information channel by an attacker is reduced.

Description

technical field [0001] The invention belongs to the technical field of on-chip multiprocessor task mapping algorithms and hardware security, and in particular relates to the design of a task mapping method aimed at information security of multi-core processors. Background technique [0002] In recent years, scholars have proposed numerous defense techniques to protect chips from side-channel attacks, and these techniques can be roughly divided into two categories, one is hardware-based defense techniques, and the other is software-based defense techniques. [0003] Hardware-based defense technology involves the design and implementation of logic. In other words, it is at the circuit design level to realize the decoupling of chip operation and side channel leakage. For example, integrating a series of dedicated capacitors between the power supply network and logic gates, or designing distributed on-chip voltage regulators, these two techniques effectively reduce information l...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/55
CPCG06F21/556
Inventor 王坚陈哲郭世泽杨鍊
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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