High stability sram storage unit circuit based on shared transfer tube

Abstract

The invention relates to a highly stable SRAM storage unit circuit based on a shared transfer tube, which belongs to the technical field of integrated circuits. The SRAM storage unit circuit proposed by the present invention, combined with the read-write mode of the circuit, makes the present invention have higher read noise tolerance and write margin; at the same time, the present invention is based on the design of the shared transmission tube, and stores the SRAM proposed by the present invention When unit circuits form a memory array, adjacent SRAM memory unit circuits in the same column are connected to the same shared bit line BLS, and a shared bit line BLS can be connected to 2-4 SRAM memory unit circuits, which is conducive to reducing the area of ​​the memory ; Applying the present invention to a bit interleaved array can solve the half-selection problem and improve the soft error rate of the memory.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a highly stable SRAM storage unit circuit based on a shared transfer tube. Background technique [0002] Reducing the power supply voltage can significantly reduce the power consumption of the circuit, especially for static random access memory (SRAM) such a circuit with high density integration. However, as the power supply voltage decreases, the memory cell is more significantly affected by process fluctuations, which reduces the read / write stability of the memory cell or even causes errors, which imposes higher requirements on the design of the memory cell. At the same time, with the continuous reduction of process size and the increase of storage capacity, the soft error rate of the memory is getting higher and higher; and the use of traditional error correction coding technology can only solve the soft error rate per bit. After the nanometer level, the soft erro...

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Problems solved by technology

However, the use of the bit interleaving structure will cause a half-selection problem, which will reduce the stability of the half-selection unit, and even destroy the original storage state of the memory.

[0003] At present, the mainstream unit of SRAM is 6T structure, such as figure 1 Shown is a schematic diagram of the traditional 6T SRAM storage unit circuit structure. In order to make the 6T unit more stable, the size of the tube can be optimized, but the read and write capabilities of the optimized 6T tube can be limited. If the 6T unit is used for bit interleaving In the structure, it will cause half-selection problems, making it difficult to work at lower voltages

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