A sram memory cell circuit with high read noise tolerance

Abstract

An SRAM storage unit circuit with high read noise tolerance belongs to the technical field of integrated circuits. The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor and the word line, its drain is used as a shared transmission terminal, and its source is connected to the second PMOS transistor, the third PMOS transistor, the fourth NMOS transistor and the sixth NMOS transistor The gate of the gate and the drains of the first PMOS transistor and the third NMOS transistor; the drain of the second NMOS transistor is connected to the bit line, and the source is connected to the gates of the first PMOS transistor and the fifth NMOS transistor and the third PMOS transistor and the third NMOS transistor. The drain of the sixth NMOS transistor; the source of the second PMOS transistor is connected to the source of the first PMOS transistor and connected to the power supply voltage, and its drain is connected to the grid of the third NMOS transistor, the source of the third PMOS transistor and the fourth The drain of the NMOS transistor; the drain of the fifth NMOS transistor is connected to the source of the third NMOS transistor, and its source is connected to the sources of the fourth NMOS transistor and the sixth NMOS transistor and grounded. The invention has higher reading noise tolerance, can solve the half-selection problem, and can improve the soft error rate problem of the memory when used in the bit interleaved array structure.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an SRAM storage unit circuit with high read noise tolerance, which can be applied to a bit interleaving structure to solve the half-selection problem. Background technique [0002] In recent years, application fields represented by wireless sensor networks and medical electronic equipment have higher and higher requirements for power consumption and performance of SoCs. Embedded static random access memory (SRAM) is one of the key components of SoCs. Reducing the power supply voltage is an effective means to ensure low power consumption of SRAM. However, the reduction of power supply voltage will bring some bad effects, such as reducing the stability of reading and writing. Therefore, one of the criteria for designing low-voltage SRAM is to improve the reading and writing of cells. performance. [0003] Another criterion for low-voltage SRAM cell design is to solve t...

AI Technical Summary

Problems solved by technology

[0004] At present, the mainstream unit of SRAM is 6T structure, such as figure 1 Shown is a schematic diagram of the circuit structure of a traditional 6T SRAM storage unit. When 6T is used in a bit-interleaved structure, it will cause a half-selection problem. At a lower voltage, the write operation becomes difficult.

Certain design needs can be met by adjusting the device size, but it has become unrealistic to achieve the design goal simply by adjusting the device size, and the improvement of the read noise margin and the improvement of the write margin are contradictory

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