A sram memory cell circuit with high stability and low static power consumption

Abstract

An SRAM storage unit circuit with high stability and low static power consumption belongs to the technical field of integrated circuits. The present invention proposes a kind of SRAM memory unit circuit of 10T structure, combines the reading and writing mode based on this circuit, can make the present invention have high read noise tolerance and writing margin; Because only one bit line in the present invention, and this In the structure of the invention, the first NMOS transistor and the third NMOS transistor are stacked to form a pull-down path, and the second PMOS transistor and the fourth PMOS transistor are stacked to form a pull-up path, which reduces the leakage current in the present invention, thereby reducing the present invention. The static power consumption of the invention; at the same time, the invention can solve the half-selection problem, and can improve the memory soft error rate problem when used in a bit interleaved array structure.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an SRAM storage unit circuit with high stability and low static power consumption. Background technique [0002] Reducing the power supply voltage can significantly reduce the power consumption of the circuit, especially for high-density integrated circuits such as SRAM (Static Random-Access Memory, static random access memory). However, as the power supply voltage decreases, the memory cells are more significantly affected by process fluctuations, resulting in reduced read / write stability of the memory cells and even errors, which impose higher requirements on the design of the memory cells. At the same time, with the continuous shrinking of the process size and the increase of the storage capacity, the soft error rate of the memory becomes higher and higher. The traditional error correction coding technology can only solve the soft error rate of a single bit, and a...

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Problems solved by technology

[0003] At present, the mainstream unit structure of SRAM storage unit is 6T structure, such as figure 1 The schematic diagram of the circuit structure of the traditional 6T SRAM storage unit is shown. In order to make the 6T structure of the SRAM storage unit have higher stability, the size of the tube can be optimized, but the reading and writing of the tube of the optimized 6T structure of the SRAM storage unit The ability to improve is limited, and due to the competition between the data to be written and the saved data value, the write operation is prone to failure at low voltage; in addition, the traditional 6T-structured SRAM storage unit used in the bit-interleaved structure will cause Reading and writing semi-choice questions

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