Satellite-borne in-orbit reconfigurable FPGA software-based verification test system

Abstract

The invention discloses a verification system used for satellite-borne FPGA reconfigurable software verification. To-be-tested target codes with different implementation forms, different scales and different complexity levels can be subjected to verification testing. The verification test system can comprise a satellite system / an upper computer, a main control board and a test board.

Description

technical field [0001] The invention relates to the field of computer software verification test, in particular to a verification test system based on on-orbit reconfigurable FPGA software. Background technique [0002] Field programmable logic device (FPGA) technology has achieved amazing development in the past few decades. The fundamental reason is that FPGA can not only solve the problems of electronic system miniaturization, low power consumption, and high reliability, but also has a short development cycle. , less investment in developing software, and the continuous reduction of chip prices have prompted FPGAs to increasingly replace ASICs in the market, especially for small-batch and multi-variety products, making FPGAs the first choice. [0003] Since there is currently no effective support for the implementation of FPGA reconfigurable verification tests systematically, different reconfiguration verification test methods are often used for different FPGA software re...

AI Technical Summary

Problems solved by technology

[0004] For the actual verification test requirements of reconfigurable FPGAs on the star, almost all verification tests can only be realized through simulation, and it is impossible to carry out unified verification tests for different chip models. At the same time, due to the particularity of reconfigurable FPGA software, it is necessary to treat The different reconfiguration software needed to configure the FPGA needs to be verified and tested in a unified manner. At this stage, only a single software verification test can be realized through simulation means, and it is impossible to truly realize the whole process of reconfigurable FPGA software to follow the verification test.

Moreover, it is very difficult to adjust the dynamic configurable test stimulus for the characteristics of the on-board reconfigurable FPGA software.

At present, there is no targeted efficient general verification system for on-board reconfigurable FPGA software verification

Images