VLSI global layout model establishing method based on explicit solution of Poisson equation

Abstract

The invention relates to a VLSI global layout model establishing method based on an explicit solution of a Poisson equation, comprising: representing the circuit as a hypergraph model; simulating theVLSI circuit layout model as a two-dimensional electrostatic system, and converting the density constraint into the constraint of the total potential energy N(v) equal to 0 of the electrostatic system; establishing partial differential equations based on the Poisson equation, boundary conditions and compatibility conditions; establishing an analytical formula of density functions and substitutinginto the partial differential equations; determining expressions of the potential and electric field according to the density functions; determining the convergence of the expressions of the potentialand electric field; solving the expressions of the potential and electric field according to the partial sum; obtaining the potential and electric field values of each grid by the fast calculation method, obtaining the potential and electric field of the module by weighting, and establishing the VLSI circuit layout model under the action of electric field force. The invention may provide an efficient and practical global layout result, and especially for large-scale examples, may meet the requirements of the current VLSI global layout stage.

Description

technical field [0001] The invention relates to the technical field of VLSI physical design automation, in particular to a method for establishing a VLSI global layout model based on the explicit solution of the Poisson equation. Background technique [0002] As technology development enters the deep nanometer era of billion-transistor integration, the performance of layout tools dominates the overall quality of EDA tools. Therefore, in recent times, many placers have been developed. There are three main layout algorithms: simulated annealing-based methods, partition-based methods, and analysis-based methods. Recent studies have shown that analytical placers usually achieve better placement quality and are scalable. [0003] In analysis-based layout, a key technique is to reduce the overlap between modules and obtain a uniformly dispersed layout. For analysis-based layout, many literatures propose overlapping reduction methods, such as partitioning, cell movement, frequen...

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Problems solved by technology

For example, the Lorentz force expression is suitable and accurate in finite element simulation, but not suitable for calculation

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