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Global Layout Optimization Method for Integrated Circuits Based on Generalized Augmented Lagrangian

A global layout and integrated circuit technology, applied in CAD circuit design, electrical digital data processing, instruments, etc., can solve the problem of slow speed of scattered units, achieve the effect of line length optimization, strong robustness, and guaranteed speed

Active Publication Date: 2022-07-15
FUZHOU UNIV
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Problems solved by technology

However, the augmented Lagrange method diffuses the unit slower than the quadratic penalty method
Furthermore, without an exact line search, the augmented Lagrangian method does not obtain a solution close enough to the stagnation point of the original problem

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  • Global Layout Optimization Method for Integrated Circuits Based on Generalized Augmented Lagrangian
  • Global Layout Optimization Method for Integrated Circuits Based on Generalized Augmented Lagrangian
  • Global Layout Optimization Method for Integrated Circuits Based on Generalized Augmented Lagrangian

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Embodiment Construction

[0013] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments.

[0014] The present invention provides an integrated circuit global layout optimization method based on generalized augmented Lagrangian, which comprises the following steps:

[0015] Step S1: represent the circuit as a hypergraph H={V, E}; each unit in the circuit is regarded as a vertex; each net is regarded as a hyperedge; where V={v 1 , v 2 ,...,v n } is the set of n units; E={e 1 , e 2 ,...,e m } is a set of m nets; n, m are natural numbers; step S2: provide a generalized augmented Lagrangian method, and use it to solve the VLSI global layout problem; step S3: prove the generalized augmentation proposed in step S2 The Lagrangian method is globally convergent for the global layout problem; Step S4: apply the generalized augmented Lagrangian method to deal with the global layout problem with line network congestion degree constraints.

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Abstract

The present invention provides an integrated circuit global layout optimization method based on generalized augmented Lagrangian, which includes the following steps: Step S1: representing the circuit as a hypergraph; each unit in the circuit is regarded as a vertex; each unit in the circuit is regarded as a vertex; The net is regarded as a hyperedge; Step S2: Provide a generalized augmented Lagrangian method and use it to solve the VLSI global layout problem; Step S3: Prove that the generalized augmented Lagrangian method is suitable for the global layout problem is globally convergent; step S4: apply the generalized augmented Lagrangian method to deal with the global layout problem with the constraints of the grid congestion. The invention retains the advantages of the quadratic penalty method and the augmented Lagrangian method, and smoothly transitions the quadratic penalty method to the augmented Lagrangian method. When this method is used to solve the global placement problem, the cells can diffuse rapidly in the "second penalty" stage and provide a good initial solution for the "augmented Lagrangian" stage, resulting in high-quality results.

Description

technical field [0001] The invention belongs to the technical field of VLSI physical design automation, and in particular relates to a generalized augmented Lagrangian-based integrated circuit global layout method. Background technique [0002] Layout is an important part of the physical design automation of Very Large Seale Integration (VLSI), and its performance quality greatly affects the downstream stages of grid design: clock tree synthesis, power optimization, global and detailed routing , layout simulation, design changes, etc. In addition, modern advanced circuit design brings many new requirements and constraints, such as routability, time, power, and manufacturability. Therefore, for modern circuit designs with millions of cells, there is a need to develop an efficient, high-quality, and robust placement algorithm. [0003] Layout algorithms can be divided into three main categories: minimum cut partition based layout methods, simulated annealing based methods, a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/392G06F30/398G06F115/06
CPCG06F30/392G06F2115/06
Inventor 陈建利朱自然朱文兴
Owner FUZHOU UNIV
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