Mixed height unit layout design method based on minimum implantation region constraint

Abstract

The invention provides a mixed height unit layout design method based on a minimum implantation region constraint. The method comprises the following steps: step S1, fast global layout; step S2, applying graph-based clustering and reshaping to the horizontal MIA conflict units; step S3, legalization of the constraint based on the MIA; and step S4: allocation and optimization of the unit position.The HVT / LVT units with the same voltage are placed closer together by adding a weighted virtual wire network. The variation of the line length can be globally minimized by depicting the Vdd / Vss constraint through the cost function and conjugate gradient solution. The regional area can be compressed and the use of packing can be reduced by using graph-based clustering method and matching-based method. The constraint based on the vertical MIA is transformed into QP problem and solved by the MMSIM solver. In order to further optimize the layout result, unit allocation and unit position optimization are also carried out finally.

Description

Technical field [0001] The invention belongs to the field of VLSI physical design automation technology, and provides a hybrid height cell layout design method based on minimum implantation area constraints. Background technique [0002] In traditional circuit design, in order to facilitate design and optimization, standard cells usually have the same height. However, in modern circuit design, the use of standard cells with different row heights can achieve a better design trade-off between delay, power, and deployability. Specifically, higher units can give greater driving force and better deployability, but at the same time it also needs to spend more area and power costs. Due to the heterogeneous cell structure (causing more global cell interference and an increase in the solution space), the circuit design of this mixed-height cell is more challenging. Moreover, in this layout design, additional consideration needs to be given to aligning the multiple-row height cells to th...

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Problems solved by technology

However, with the reduction of cell feature size, and due to the limitation of lithography technology, the layout of multi-threshold voltage cells may violate the MIA constraints.

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