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Method for spatial memory stream prefetching engine, apparatus, manufacture method and test method

A memory string and stream prefetching technology, applied in memory systems, instruments, machine learning, etc., can solve the problems of lack of stable confidence mechanism, loss of timeliness, inability to handle pattern shift alignment, etc.

Pending Publication Date: 2018-11-23
SAMSUNG ELECTRONICS CO LTD
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  • Abstract
  • Description
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Problems solved by technology

[0008] However, the spatial memory streaming scheme has several disadvantages
Spatial memory streaming cannot handle shift alignment of patterns with respect to line boundaries between caches
In addition, spatial bit vectors are often used to access spatial patterns at a greater granularity per access and cannot track temporal order
Spatial memory streaming also lacks a robust confidence mechanism and is not dynamically adaptable, i.e. spatial memory streaming cannot adapt to program phase changes when dynamic branching behavior changes offset patterns, for example
These disadvantages lead to reduced coverage and accuracy, loss of timeliness, thereby reducing performance and increasing power consumption

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  • Method for spatial memory stream prefetching engine, apparatus, manufacture method and test method
  • Method for spatial memory stream prefetching engine, apparatus, manufacture method and test method
  • Method for spatial memory stream prefetching engine, apparatus, manufacture method and test method

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Embodiment Construction

[0077] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that although the same elements are shown in different drawings, the same elements are designated by the same reference numerals. In the following description, only specific details such as detailed configuration and components are provided to help the general understanding of the embodiments of the present disclosure. It is therefore apparent that various changes and modifications of the embodiments described herein can be made by those skilled in the art without departing from the scope of the present disclosure. Also, descriptions of well-known functions and constructions are omitted for clarity and conciseness. Terms described below are terms defined in consideration of functions in the present disclosure, and may vary according to a user, user's intention, or custom. Therefore, definitions of terms should be determined bas...

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Abstract

The invention describes a method for a spatial memory stream prefetching engine, an apparatus, a manufacture method and a test method. In one aspect, the spatial memory stream prefetching engine usestrigger-to-trigger stride detection to make training table entries to be pattern history table entries and to drive spatially related prefetching in regions of greater distance. In the other aspect, the spatial memory stream prefetching engine maintains a blacklist of program counter values to not be used as trigger values. In another aspect, the spatial memory stream prefetching engine uses, forexample, a filter table, a training table, and a hash value of a particular field of the trigger program counter in an entry in the pattern history table as an index value for a table.

Description

[0001] priority [0002] This application claims priority to U.S. Application Serial No. 15 / 690,931, filed August 30, 2017, and to U.S. Provisional Patent Application Serial No. 62 / 505,318, filed May 12, 2017 and 7, 2017 Priority to U.S. Provisional Patent Application Serial No. 62 / 535,460, filed May 21, all applications are incorporated herein by reference in their entirety. technical field [0003] The present disclosure relates generally to processor memory management, and more specifically, to spatial memory stream confidence mechanisms. Background technique [0004] A computer processor performs cache prefetching to store instructions or data by fetching instructions or data from its initial storage in slower memory (i.e., with slower read / write times) to a faster location before the instruction or data actually needs to be fetched. Faster local memory (ie, has faster read / write times and is often located closer to the instruction / data pipeline) to enhance execution pe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/0877G06N20/00
CPCG06F9/383G06F12/0862G06F12/0877G06N20/00G06F2212/452G06F2212/6024G06F12/0875Y02D10/00G06F2212/62G06F9/30043G06F9/3802G06F12/0811G06F3/06
Inventor 艾德华·A·柏瑞柯本艾伦·瑞达克里斯纳
Owner SAMSUNG ELECTRONICS CO LTD
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