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Cache replacement method and device thereof, and heterogeneous multi-core system

A cache replacement and heterogeneous multi-core technology, applied in the field of data processing, can solve problems such as limited capacity, and achieve the effect of improving utilization, computing power and computing speed

Inactive Publication Date: 2018-12-18
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Under the multi-level cache architecture, although the capacity of the last-level shared cache is large, its capacity is also limited. Sharing the last-level cache by multiple different types of processors will cause competition for cache resources. Therefore, the utilization of cache Rate is an important factor affecting the computing power and computing speed of heterogeneous multi-core systems

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  • Cache replacement method and device thereof, and heterogeneous multi-core system
  • Cache replacement method and device thereof, and heterogeneous multi-core system
  • Cache replacement method and device thereof, and heterogeneous multi-core system

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Embodiment Construction

[0058] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with aspects of the invention as recited in the appended claims.

[0059] figure 1 is a schematic diagram of the architecture of a heterogeneous multi-core system, such as figure 1 As shown, the heterogeneous multi-core system includes a plurality of processors, which are two CPUs (respectively CPU0 and CPU1) and two GPUs (respectively GPU0 and GPU1), and each processor is, for example, a single-core processor , each processor has its own independent private ...

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Abstract

The invention provides a cache replacement method, which is applied to a heterogeneous multi-core system. The method comprises the following steps: when it is determined that a first application program currently running is an application program running on a GPU; determining a running type of the first application according to a performance parameter of the first application; determining a cachepriority of first data accessed by the first application according to a running type of the first application, the cache priority of the first data including a priority other than a highest priority;determining a cache replacement algorithm according to the algorithm type identification of the record; caching the first data into a cache queue of the shared cache according to the determined cachereplacement algorithm and a cache priority of the first data. The cache replacement method can improve the utilization rate of cache while ensuring the performance of GPU, which is helpful to improvethe computing power and computing speed of heterogeneous multi-core system.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a cache replacement method and device thereof, and a heterogeneous multi-core system. Background technique [0002] A heterogeneous multi-core system refers to the integration of multiple single-core or multi-core processors of different types on a chip, which has the characteristics of small size and high computing performance. [0003] In a heterogeneous multi-core system, a multi-level cache is usually used, each processor has its own independent private level-1 or multi-level cache Cache, and all processors have a shared cache (called a shared cache), and the shared cache is multiple Commonly used by processors, usually the last level of cache; under multi-level cache, when the processor processes data, it can first read data from the level-1 cache closest to the processor. When there is more data, it is read from the caches of the following levels in turn. When ther...

Claims

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Application Information

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IPC IPC(8): G06F12/0811
CPCG06F12/0811G06F12/126G06F9/544G06F12/0842G06F12/123G06T1/60
Inventor 范清文苗京花张浩陈丽莉王立新赵斌孙玉坤王雪丰李茜李文宇彭金豹索健文
Owner BOE TECH GRP CO LTD