Output timing jitter estimation method based on pseudo-drain open-circuit termination

Abstract

The invention discloses an output device timing jitter estimation method based on pseudo-drain open circuit termination, which mainly solves the problem that the time consumption of violence simulation is too long when the data link timing jitter is estimated in the prior art. The realization scheme is as follows: 1. extracting the current and voltage data of the semiconductor transistor of the output device and calculating the transconductance parameters; 2. calculating and solving the differential equation of the voltage initial state and the output voltage of the transconductance parametercolumn; 3. according to the initial state of the voltage and the output voltage, calculating the error sequence of the sequence interval caused by the power supply noise and the ground noise; 4, calculating the transfer function from the noise to the timing jitter from the time interval error sequence and the noise spectrum; 5. multiplying the transfer function with the simulated power noise spectrum and obtaining the time-domain timing jitter estimation by inverse Fourier transform. The timing jitter estimation of the invention belongs to the numerical calculation, and has less time consumption than the violent simulation, obtains rich transfer functions in the frequency domain, facilitates the estimation of the timing jitter, and can be used for the design of the communication link.

Description

technical field [0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a timing jitter estimation method of an output device, which can be used in the design of communication links. Background technique [0002] At present, as the speed of the data transmission interface of the electronic circuit reaches several gigabits per second, under the premise of satisfying the bit error rate, the timing tolerance continues to decrease with the increase of the data rate, and the timing jitter will cause a bit error at the receiver. The increase in the rate affects the reliability of data communication, and timing jitter has become a challenge for high-speed interface design. Timing jitter can be classified into deterministic jitter and random jitter, and further jitter can be divided into data-dependent jitter, boundary-independent jitter, periodic jitter and Gaussian jitter, while power supply noise is an important source of determini...

AI Technical Summary

Problems solved by technology

This simulation method is still very time-consuming, and the worst-case eye diagrams of many input and output links cannot be excited by a code stream with a certain code length.

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