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Buffer reinforcement method and device capable of resisting side channel attack

A side-channel attack and caching technology, applied in computer security devices, instruments, electrical digital data processing, etc., can solve the problem that low-privileged software cannot access high-privileged software system registers or memory, and achieves a wide range of applications and good compatibility. , the effect of small hardware overhead

Active Publication Date: 2018-12-18
PHYTIUM TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Under these hardware privilege protection mechanisms, low-privileged software usually cannot access system registers or memory of high-privileged software

Method used

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  • Buffer reinforcement method and device capable of resisting side channel attack
  • Buffer reinforcement method and device capable of resisting side channel attack
  • Buffer reinforcement method and device capable of resisting side channel attack

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 2

[0062] This embodiment is basically the same as Embodiment 1, and the main difference is that a unified hardware control bit SC_HARDEN_EN_G is added to control whether to execute a corresponding hardening strategy.

[0063] The implementation steps of the buffer reinforcement method that can resist side channel attacks in this embodiment include:

[0064] 1) Read the unified hardware control bit SC_HARDEN_EN_G; obtain the operation request for the cache, and the cache entry contains the allocator identification ALLOCATOR field; when the operation request is an allocation entry, jump to step 2); when the operation When the request is to access an entry, skip to step 3); when the operation request is to replace an entry, skip to step 4);

[0065] 2) For the operation request allocation entry, if the hardware control bit SC_HARDEN_EN_G is turned on, the allocation cache hardening strategy is executed: fill in the identifier of the currently running software domain of the processo...

Embodiment 3

[0069] This embodiment is basically the same as Embodiment 1, and the main difference is that a hardware control bit SC_HARDEN_EN_TLB corresponding to the cache is added to control whether the cache or a modified cache implements a corresponding hardening strategy.

[0070] The implementation steps of the buffer reinforcement method that can resist side channel attacks in this embodiment include:

[0071] 1) Obtain the operation request for the cache, read the hardware control bit SC_HARDEN_EN_TLB corresponding to the target cache of the current operation request, and the cache entry contains the allocator identification ALLOCATOR field; when the operation request is an allocation entry, jump Execute step 2); when the operation request is to access an entry, skip to step 3); when the operation request is to replace an entry, skip to step 4);

[0072] 2) For the operation request allocation entry, if the hardware control bit SC_HARDEN_EN_TLB is enabled, the allocation cache har...

Embodiment 4

[0076] This embodiment is basically the same as Embodiment 1. The main difference is that the unified hardware control bit SC_HARDEN_EN_G and the hardware control bit SC_HARDEN_EN_TLB corresponding to the cache are added, and the hardware control bit SC_HARDEN_EN_TLB corresponding to the unified hardware control bit cache is used to control the Whether the cache or modified cache implements the corresponding hardening strategy.

[0077] The implementation steps of the buffer reinforcement method that can resist side channel attacks in this embodiment include:

[0078] 1) Read the unified hardware control bit SC_HARDEN_EN_G; obtain the operation request for the cache, read the hardware control bit SC_HARDEN_EN_TLB corresponding to the target cache of the current operation request, and the entry of the cache contains the allocator identification ALLOCATOR field; when the operation When the request is to allocate an entry, skip to step 2); when the operation request is to access ...

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Abstract

The invention discloses a buffer reinforcement method and device capable of resisting side channel attack. An allocator identification ALLOCATOR field is added in each buffer list item of the invention. Whenever an entry is allocated in the cache, the identity of the currently running software domain of the processor is populated into the ALLOCATOR field of the allocated entry; when accessing thecache, the cache entry is hit only if the identity of the currently running software domain of the processor is the same as the ALLOCATOR field in the cache entry; when replacing the existing entriesin the cache, if the cache entries to be replaced are invalid or the identifiers of the ALLOCATOR field and the software domain currently running by the processor are the same, the cache entries can be replaced directly; otherwise the entire cache is emptied. The invention can realize the reinforcement of the cache in the processor with less hardware, resist the side channel attack aimed at the cache, and improve the safety of the processor.

Description

technical field [0001] The invention relates to cache management technology in a microprocessor, in particular to a cache reinforcement method and device capable of resisting side channel attacks. Background technique [0002] Cache is a device widely used in microprocessors. Its main function is to save some common information during program execution, such as instruction code, data, virtual and real address mapping, branch direction bias history, branch target address history, etc. By keeping this information in the cache on the microprocessor chip, you can reduce the latency of accessing them, avoid the energy consumption caused by obtaining this information off-chip, or reduce the pause time of the processor pipeline, so as to improve performance or reduce power consumption. consumption purpose. figure 1 Shown is the general structure of the cache in the processor, each cache item includes Tag, attribute and data. [0003] The cache involved in the present invention in...

Claims

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Application Information

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IPC IPC(8): G06F21/55
CPCG06F21/556G06F2221/034
Inventor 窦强赵天磊张承义高军薛洪波刘晓燕王玉姣丁哲
Owner PHYTIUM TECH CO LTD