A multi-phase clock generation circuit with random disturbance

Abstract

The invention discloses a multi-phase clock generation circuit added with random disturbance. The clock generation circuit comprises a main clock module, a random signal generation module and a buffermatrix switch module. The main clock module is used for generating N polyphase clock signals; the buffer matrix switch module is used for randomly switching the transmission paths of the input N multi-phase clock signals under the control of the random control signals output by the random signal generation module, and outputting N multi-phase clock signals added with random disturbances. By adding random disturbance, the clock phase error is whitened. With only a small loss of signal-to-noise ratio, the influence of polyphase clock phase error on the performance of high precision TI ADC in real time can be eliminated, which can track and eliminate the influence of clock phase error fluctuation with the change of working environment, whiten the error spurious component at the fixed frequency to the noise floor without interrupting the normal operation of the TI ADC, and has the advantages of simple design and implementation, high stability.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and relates to a clock generation circuit, more specifically, to a multi-phase clock generation circuit with random disturbance added. Background technique [0002] In time-interleaved data converters (TI ADCs), the phase accuracy of multiphase clocks directly affects system performance, while multiphase clock generation circuits are often affected by factors such as process deviations and circuit mismatches, and inevitably have phase errors. For In a high-precision TI ADC, the clock phase error will lead to a significant drop in the dynamic performance SFDR, at k f s / L±f in (f s is the TI ADC sampling frequency, f in is the frequency of the input signal, L is the number of integrated channels of TI ADC, k=1,2,...,L-1) there are error spurious components, which need to be corrected. At present, the conventional method of eliminating the clock phase error usually adopts the method of foregr...

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Problems solved by technology

[0003] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a multi-phase clock generation circuit adding random disturbances, which is used to solve the current existing TI ADC clock phase error elimination technology, which has high design and implementation complexity, The problem of limited stability and reliability or the inability to track and eliminate the clock phase error in real time as the working environment changes

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