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A 3D NAND memory and its manufacturing method

A manufacturing method and memory technology, which is applied in the field of memory, can solve the problems of relatively difficult etching of the common source of memory arrays, poor film uniformity, and difficult etching process of memory layers, etc., so as to improve the structure or stress. , Improve the uniformity of the film and reduce the difficulty of the etching process

Active Publication Date: 2020-12-04
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] 1. Due to the docking of multiple stacked structures, the aspect ratio of the channel hole is large, so the etching process of the memory layer at the bottom of the channel hole is relatively difficult
[0005] 2. Similarly, due to the channel hole with a large aspect ratio, it is also difficult to etch the common source of the storage array of the 3D NAND memory
[0006] 3. In addition, the functional layers in the channel holes of the upper and lower stacked structures are all formed through a one-step process after being stacked together, resulting in poor film uniformity and structural or stress problems

Method used

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  • A 3D NAND memory and its manufacturing method
  • A 3D NAND memory and its manufacturing method
  • A 3D NAND memory and its manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0082] See Figure 1 to Figure 2(16) , the manufacturing method of the 3D NAND memory provided in Embodiment 1 of the present application includes the following steps:

[0083] S101: forming a first stack structure on a substrate, where the first stack structure includes a first channel hole penetrating through the first stack structure.

[0084] As shown in FIG. 2( 1 ), a first stack structure 20 is formed on the substrate 10 , and the first stack structure 20 includes a first channel hole CH1 penetrating through the first stack structure 20 . Wherein, the first stack structure 20 may be formed by stacking interlayer insulating layers 201 and sacrificial layers 202 alternately.

[0085] In order to form the common source of the memory cells, an epitaxial structure 203 epitaxially grown from the substrate 10 is formed at the bottom of the first channel hole CH1 . The epitaxial structure 203 can be used as a common source of the memory array.

[0086] It should be noted that...

Embodiment 2

[0169] See Figure 4 to Figure 5(3) The manufacturing method of the 3D NAND memory provided in the second embodiment of the present application includes the following steps:

[0170] S401: Form a first stack structure on the substrate, the first stack structure includes a first channel hole penetrating through the first stack structure, the top layer of the first stack structure is a polysilicon layer, or the top layer is an insulating layer, and the second top layer is the gate material layer.

[0171] As shown in FIG. 5( 1 ), a first stack structure 20 is formed on the substrate 10 , and the first stack structure 20 includes a first channel hole CH1 penetrating through the first stack structure 20 . Wherein, the first stacked structure 20 may be formed by alternately stacking interlayer insulating layers 201 and sacrificial layers 202 , and the second top layer of the first stacked structure is a polysilicon layer 209 , and the top layer is an insulating layer 210 .

[017...

Embodiment 3

[0180] It should be noted that Embodiment 3 can be improved on the basis of Embodiment 1 or Embodiment 2 above. As an example, this application is improved on the basis of Embodiment 1.

[0181] See Figure 6 to Figure 7(4) The manufacturing method of the 3D NAND memory provided in the third embodiment of the present application includes the following steps:

[0182] S601 to S609 are the same as S101 to S109, and will not be described in detail here for the sake of brevity.

[0183] S610: Form an etch stop layer above the plug structure.

[0184] As shown in FIG. 7( 1 ), an etch stop layer 34 is formed above the plug structure 32 . As an example, the material of the etch stop layer 34 may be metal tungsten.

[0185] S611: forming a second stack structure above the etching stop layer and the gate connection layer.

[0186] As shown in FIG. 7( 2 ), a second stack structure 40 is formed on the etching stop layer 34 and the gate connection layer 30 .

[0187] S612: Etching th...

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Abstract

The application discloses a 3D NAND memory and a manufacturing method thereof. In this method, the functional layers in the channel holes in the first stacked structure and the second stacked structure that are docked together are formed separately, instead of being formed simultaneously through a one-step process after the docking. Therefore, when forming the second stacked structure Before, the memory layer at the bottom of the first stack structure was etched away. Compared with the aspect ratio of the channel holes of the upper and lower two-layer stack structures, the aspect ratio of the channel holes of the stack structure is half smaller. Therefore, this The method provided by the application can reduce the difficulty of the etching process of the memory layer at the bottom of the channel hole, and similarly, can also reduce the difficulty of the etching process of the common source of the storage array. In addition, in the method provided in the present application, the functional layers in the channel holes of the upper and lower stacked structures are formed separately, so that the uniformity of the film is improved, and problems in structure or stress are improved.

Description

technical field [0001] The present application relates to the technical field of memory, in particular to a 3D NAND memory and a manufacturing method thereof. Background technique [0002] 3D NAND memory is a flash memory device with a three-dimensional stack structure, and its storage core area is composed of alternately stacked metal gate layers and interlayer insulating layers combined with vertical channel holes. Under the condition of the same area, the more metal gate layers stacked vertically, the higher the storage density and capacity of the flash memory device. The number of stacked layers of word lines in common storage structures can reach tens to hundreds of layers. [0003] In order to increase the storage density of 3D NAND memory, stacked 3D NAND memory has emerged. The stacked 3D NAND memory is formed by butting together at least two stacked structures. At present, in the manufacturing process of stacked 3D NAND memory, the functional layer of the memory ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11578H10B43/20
CPCH10B43/20
Inventor 刘峻霍宗亮
Owner YANGTZE MEMORY TECH CO LTD