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A parallel architecture method and apparatus for use in MR hybrid reality devices

A mixed reality and device technology, applied in machine execution devices, architectures with a single central processor, concurrent instruction execution, etc., can solve problems such as slow data processing

Pending Publication Date: 2019-02-05
幻视互动(北京)科技有限公司
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  • Claims
  • Application Information

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Problems solved by technology

[0005] The present invention provides a parallel architecture method and device used in MR mixed reality equipment to solve the problem of slow data processing in MR equipment in the prior art

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  • A parallel architecture method and apparatus for use in MR hybrid reality devices
  • A parallel architecture method and apparatus for use in MR hybrid reality devices
  • A parallel architecture method and apparatus for use in MR hybrid reality devices

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Embodiment Construction

[0024]In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0025] figure 1 A flow chart of a parallel architecture method applied on an MR mixed reality device provided by an embodiment of the present invention, such as figure 1 shown, including:

[0026] Step 101, the reconfigurable processor receives the data stream and performs data processing on it to obtain a data set.

[0027] Step 102, the r...

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Abstract

The invention provides a parallel architecture method and device applied to MR hybrid reality device, which receives and processes real-time data streams through a reconfigurable processor, analyzes the real-time data streams into instructions and image data, and sends the instructions and image data to corresponding processors. The graphics image processor performs real-time rendering on the graphics image data and simultaneously receives display instructions from the central processing unit to display the images. The invention has the advantages of adopting the heterogeneous parallel form ofthe combination of the central processor, the graphics image processor and the reconfigurable processor, and realizing the high-speed processing of the data stream by utilizing the high concurrency,low power consumption and reconfigurable characteristics of the reconfigurable processor. The graphics image processor and the reconfigurable processor process the data stream in parallel according tothe instruction data, thereby improving the processing speed of the data, solving the problem of slow processing of the MR device data in the prior art, and reducing the time overhead and power consumption for processing such tasks. So that the images displayed by the MR device can be more real-time and the user experience can be improved.

Description

technical field [0001] The present invention relates to the field of mixed reality data processing, in particular to a parallel architecture method and device applied to MR mixed reality equipment. Background technique [0002] In the prior art, a CPU (Central Processing Unit, central processing unit) and a GPU (Graphics Processing Unit, graphics processing unit) are generally used for processing data streams generated during operation of MR (Mixed Reality, mixed reality) devices. In the process of processing data streams, the CPU is specifically used to process complex logic and improve the execution efficiency of instructions, so it has strong computational versatility and can handle high computational complexity, but the computational performance is average. GPU is mainly used for image processing calculations. [0003] The CPU processes data through serial processing. It queues up the received data and processes them one by one. When processing tasks that require the co...

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Application Information

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IPC IPC(8): G06F15/78G06F9/38
CPCG06F9/3885G06F15/7871Y02D10/00
Inventor 杜晶陈清甫张弦范懿文
Owner 幻视互动(北京)科技有限公司