Phase compensation method and related phase locked loop module

Abstract

The invention relates to a phase compensation method which is used for a phase locked loop module of a communication device and comprises the step of: according to an input signal, deciding to outputa maximum likelihood phase to an oscillator of the phase locked loop module, or outputting a digital assisted phase error to a filter of the phase locked loop module, wherein the maximum likelihood phase is a phase generated when known data in the input signal is estimated by utilizing a maximum likelihood method, and the digital assisted phase error is a phase error generated when the known datain the input signal is estimated by using a data assisted method.

Description

technical field [0001] The present invention refers to a phase compensation method and a related phase-locked loop module, especially a phase compensation method capable of adjusting and predicting a phase error of unknown data according to channel quality, a related phase error prediction unit and a phase-locked loop module. Background technique [0002] A Phase Locked-Loop (PLL) circuit is used to generate a periodic output signal, and the periodic output signal is expected to have a fixed phase relationship with a periodic input signal. Phase-locked loop circuits are widely used in various circuit systems, such as data and clock recovery circuits (Clock and DataRecovery), transceiver modules (Transceiver) or frequency generators (Frequency Synthesizer) of wireless communication systems. limited to this. [0003] Please refer to figure 1 , figure 1 It is a schematic diagram of a PLL circuit 10 in the prior art. The PLL circuit 10 is used to calibrate an input signal IN...

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Problems solved by technology

However, when the channel quality (such as SNR) is low, the maximum likelihood phase φ ES_ML Will greatly deviate from the real phase of the known data, but the calibration speed of the phase-locked loop circuit 10 will be greatly reduced

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