Layout structure for saving chip area and a preparation method thereof

A layout structure and chip area technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as large chip area, and achieve the effect of reducing chip cost, reducing cost, and saving area

Inactive Publication Date: 2019-02-15
广芯微电子(广州)股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The invention discloses a layout structure and a preparation method for saving chip area, an

Method used

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  • Layout structure for saving chip area and a preparation method thereof
  • Layout structure for saving chip area and a preparation method thereof
  • Layout structure for saving chip area and a preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0026] Embodiment 1, in the implementation process of chip physical design, this technical solution increases the realization of the core module of irregular shape, cuts off the corner area of ​​75umx75um in the two core modules, and then increases the length or width of the core module of irregular shape , so as to ensure that the layout area of ​​the overall irregular shape core module remains unchanged, and then the irregular shape core module can be physically realized as the ordinary core module, and then the two core modules with the corner area of ​​75umx75um cut off are placed on the two sides of the chip One corner, the cutting position is placed relative to the sealring of the chip outer frame, and the side border of the sealring can be indented by at least 75um, so that the border on the side of the sealring1 can be indented without changing the size of the core logic area of ​​the chip. The inner indentation is at least 75um, so as to reduce the chip area by changin...

Embodiment 2

[0027] Embodiment 2, increase the realization of irregularly shaped core modules, cut off the corner area of ​​75umx75um in the three core modules, and then increase the length or width of the irregularly shaped core modules, so as to ensure the layout of the overall irregularly shaped core modules The area remains the same, and then the irregular shape core module can be physically realized like the ordinary core module, and then three core modules with the corner area of ​​75umx75um cut off are placed on the three corners of the chip, and the cut position is placed relative to the sealring of the chip outer frame , so that without changing the size of the core logic area of ​​the chip, the borders on both sides of the sealring can be indented by at least 75um, thereby reducing the chip area by changing the chip structure layout. The chip area is reduced by cutting off the corner of the core module and placing the cut corner relative to the seal ring of the chip outer frame, a...

Embodiment 3

[0028] Embodiment 3, increase the realization of the core module of irregular shape, cut off the corner area of ​​75umx75um in the four core modules, and then increase the length or width of the core module of irregular shape, thereby ensuring the layout of the overall irregular shape core module The area remains the same, and then the irregular-shaped core module can be physically realized as the ordinary core module, and then the four core modules with the corner area of ​​75umx75um cut off are placed on the four corners of the chip, and the cut-off position is placed relative to the sealring401 of the chip outer frame , so that without changing the size of the core logic area of ​​the chip, the border of the sealring 401 can be indented by at least 75um, thereby reducing the chip area by changing the chip structure layout. The chip area is reduced by cutting off corners of the core module and placing the cut corners relative to the sealring 401 of the chip outer frame, and t...

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Abstract

The invention belongs to the technical field of chip layout design, in particular to a layout structure and a preparation method for saving chip area. The invention mainly relates to a chip layout structure in which the design rule is reasonably utilized in a digital money mining machine chip or a high-performance parallel computing chip, and the module shape is changed to reduce the waste of thechip corner area to the minimum in the AIO flow. By cutting off the right angle corner of the core module, the core module cutting off the right angle corner is arranged at the chip corner, and the cutting angle is placed relative to the chip sealring corner; And the area of the core module with the right angle cut is kept constant by increasing the width or length of the core module with the right angle cut. So as to realize the reduction of chip area.

Description

technical field [0001] The invention belongs to the technical field of chip layout design, in particular to a layout structure and a preparation method for saving chip area. Background technique [0002] In digital currency mining machine chips or high-performance parallel computing chips, the chip area is a very critical indicator, especially in the design of 10nm, 7nm, or more advanced technology, a little waste of area will cause chip cost and Huge loss of market competitiveness. [0003] Existing digital currency mining machine chips or high-performance parallel computing chips, because of advanced technology and huge power consumption, all adopt advanced FLIPCHIP package design. Layout io's existing layout technology solutions are divided into two types, one is PIO The solution is to place a circle of PIO pad instances outside the core area of ​​the chip. See figure 1 , where 1-seal ring; 2-chip peripheral IO device area; 3-chip core device area. The other is the ARE...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/392
Inventor 王锐李景琼
Owner 广芯微电子(广州)股份有限公司
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