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A hardware implementation method of an on-chip reconfigurable serial bus controller

A technology of serial bus and hardware implementation, which is applied to the architecture with a single central processing unit, instruments, digital computer components, etc., and can solve the problem of low reusability of serial bus controllers, waste of area, time cost, etc. problem, to achieve the effect of saving development time, saving area and saving development time

Inactive Publication Date: 2019-02-19
ZHEJIANG UNIV
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Problems solved by technology

[0003] To deal with this demand, the usual practice is that the chip will integrate different interface IPs to support the required serial bus protocol as comprehensively as possible, because these IPs are independent and do not multiplex control logic circuits, and are usually not used at the same time All serial bus controllers waste a lot of area
Sometimes to deal with peripheral devices with special needs, the chip may also need to provide a serial bus protocol that supports non-standard protocols. The reusability of serial bus controllers with standard protocols is not high

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  • A hardware implementation method of an on-chip reconfigurable serial bus controller
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  • A hardware implementation method of an on-chip reconfigurable serial bus controller

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Embodiment Construction

[0026] The present invention will be further described below in conjunction with accompanying drawing.

[0027] Such as figure 1 As shown, the flow of the hardware implementation method of the reconfigurable serial bus controller in the SoC chip of the present invention is as follows: first, multiple states are defined, and each state can control the circuit to realize the corresponding logic function. Then configure the state machine transitions and jumps corresponding to the supported communication protocols in order through software, so that the purpose of supporting different interface protocols through software configuration can be achieved, and at the same time, the control logic can be reused to the greatest extent. And the non-standard protocols needed for flexible implementation. The similar instructions configured by software are divided into two types. The first one is composed of the value of the state and the address of the corresponding jump instruction. The se...

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Abstract

The invention provides a hardware implementation method of an on-chip reconfigurable serial bus controller, which includes such steps as defining a plurality of states, realizing corresponding logic function through control circuit, sequentially configuring state machine transition and jump corresponding to supported communication protocol to support different interface protocol through software configuration, and sequentially configuring software to support different interface protocol. The present invention implements maximum multiplexing control logic to support applications such as I2C, SPI, SSP, Microwire, Enhanced SPI, IrDA 1.0 SIR, RS485, UART, ISO 7816-3 and other standard communication protocols, as well as the hardware implementation method of supporting some non-standard protocols easily through the flexible configuration, not only saves the area, but also saves the development time of a large number of non-standard protocol circuits.

Description

technical field [0001] The invention relates to the field of chips, in particular to a hardware implementation method of a reconfigurable serial bus controller in an SoC chip. Background technique [0002] The serial bus is a device used to realize the connection and data exchange between the chip and external devices. The function of the serial bus controller (interface) is to realize that the CPU connects the peripheral devices together through the serial bus. There are many types of serial bus controllers, and their corresponding interface circuits are different. Usually the chip may be connected with different peripheral devices, and the types of serial bus interfaces that different peripheral devices can provide are also different. [0003] To deal with this demand, the usual practice is that the chip will integrate different interface IPs to support the required serial bus protocol as comprehensively as possible, because these IPs are independent and do not multiplex...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78
CPCG06F15/7807G06F15/7871
Inventor 黄凯
Owner ZHEJIANG UNIV
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