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Chip package structure

A chip packaging structure and chip packaging technology, applied in the direction of electrical components, electric solid devices, circuits, etc., can solve the problems of large lift-off stress, damage, etc., and achieve the effect of improving reliability and avoiding damage

Inactive Publication Date: 2019-03-01
IND TECH RES INST +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In terms of the conductive pillars between each chip and the redistribution wiring layer in the chip packaging structure, the conductive pillars on each chip that are closest to the lift-off end will bear a relatively large lift-off stress during the lift-off process. risk of damage

Method used

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Embodiment Construction

[0045] Figure 1A is a cross-sectional view of a chip package structure according to an embodiment of the present invention. Figure 1B Yes Figure 1A Partial structural top view of the chip package structure. In order to make the drawings more clear, Figure 1A The redistribution wiring layer 130 and the underfill material 140 are not in Figure 1B is shown in . Please refer to Figure 1A and Figure 1B , the chip packaging structure 100 of this embodiment includes a chip packaging layer 110 , a conductive structure layer 120 and a redistribution circuit layer 130 . The chip encapsulation layer 110 includes a chip 112 and an encapsulant 114 , the chip 112 has an upper surface 112 a, and the encapsulant 114 covers the chip 112 and exposes the upper surface 112 a. The conductive structure layer 120 is disposed on the chip packaging layer 110 , and the redistribution circuit layer 130 is disposed on the conductive structure layer 120 and electrically connected to the chip 112...

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Abstract

A chip package structure includes a chip package layer and at least one conductive structure layer. The chip package layer includes at least one chip and an encapsulant. The chip has an upper surface,and the encapsulant is used to encapsulate the chip and expose the upper surface. The conductive structure layer includes a plurality of first conductive pillars and a plurality of second conductivepillars. The first conductive pillars are disposed on the upper surface, the second conductive pillars are disposed on the upper surface and located between an edge of the upper surface and the firstconductive pillars. A density of the second conductive pillars along an extending direction of the edge is greater than or equal to 1.2 times of a density of the first conductive pillars along the extending direction of the edge.

Description

technical field [0001] The invention relates to a chip packaging structure. Background technique [0002] In recent years, as the demand for electronic products has moved towards higher functionality, higher speed of signal transmission, and higher density of circuit components, semiconductor-related industries have also been developing day by day. In the semiconductor packaging manufacturing process of the semiconductor industry, the chip packaging structure that has not been singulated can be formed on a temporary substrate, and then the chip packaging structure is separated from the substrate. Specifically, one end of the substrate (hereinafter referred to as the lift-off end) can be pulled up to lift it off the chip package structure. In addition, one end of the chip package structure (hereinafter referred to as the lift-off end) can also be pulled up to lift it off the substrate. During the lift-off process, the substrate (or chip package structure) is gradually lifte...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L23/367H01L23/373H01L23/49H01L23/498H01L21/48H01L21/56
CPCH01L21/48H01L21/56H01L23/31H01L23/367H01L23/373H01L23/49H01L23/498
Inventor 杨镇在杨克勤庄瑞彰吴彦葶吕嘉华
Owner IND TECH RES INST
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